Real-Time Reconfigurable Processor to Detect Similarities in Compressed Video Using Generalized Hough Transformation

2020 ◽  
Vol 30 (9) ◽  
pp. 2932-2946
Author(s):  
Sergio R. Geninatti ◽  
Eduardo I. Boemo
Author(s):  
Saddam Bekhet ◽  
Amr Ahmed ◽  
Andrew Hunter

Cryptography ◽  
2020 ◽  
Vol 4 (2) ◽  
pp. 18
Author(s):  
Mohammed Abu Taha ◽  
Wassim Hamidouche ◽  
Naty Sidaty ◽  
Marko Viitanen ◽  
Jarno Vanne ◽  
...  

Video protection and access control have gathered steam over recent years. However, the most common methods encrypt the whole video bit stream as unique data without taking into account the structure of the compressed video. These full encryption solutions are time and power consuming and, thus, are not aligned with the real-time applications. In this paper, we propose a Selective Encryption (SE) solution for Region of Interest (ROI) security based on the tile concept in High Efficiency Video Coding (HEVC) standards and selective encryption of all sensitive parts in videos. The SE solution depends on a chaos-based stream cipher that encrypts a set of HEVC syntax elements normatively, that is, the bit stream can be decoded with a standard HEVC decoder, and a secret key is only required for ROI decryption. The proposed ROI encryption solution relies on the independent tile concept in HEVC that splits the video frame into independent rectangular areas. Tiles are used to pull out the ROI from the background and only the tiles figuring the ROI are encrypted. In inter coding, the independence of tiles is guaranteed by limiting the motion vectors of non-ROI to use only the unencrypted tiles in the reference frames. Experimental results have shown that the encryption solution performs secure video encryption in a real time context, with a diminutive bit rate and complexity overheads.


2021 ◽  
Author(s):  
Theepan Moorthy

The H.264 video compression standard uses enhanced Motion Estimation (ME) features to improve both the compression ratio and the quality of compressed video. The two primary enhancements are the use of Variable Block Size Motion Estimation (VBSME) and multiple reference frames. These two additions greatly increase the computational complexity of the ME algorithm, to the point where a software based real-time (30 frames per second (fps)) implementation is not possible on present microprocessors. Thus hardware acceleration of the H.264 ME algorithm is necessary in order to achieve real-time performance for the implementation of the VBSME and multiple reference frames features. This thesis presents a scalable FPGA-based ME architecture that supports real-time H.264 ME for a wide range of video resolutions ─ from 640x480 VGA to 1920x1088 High Definition (HD). The architecture contains innovations in both the data-path design and memory organization to achieve scalability and real-time performance on FPGAs. At 37% FPGA device utilization, the architecture is able to achieve 31 fps performance for encoding full 1920x1088 progressive HDTV video.


2014 ◽  
Vol 596 ◽  
pp. 355-360 ◽  
Author(s):  
Yan Yun Xing ◽  
Bo Yu ◽  
Fang Qun Yang

In order to improve the accuracy of lane mark line identifying and tracking, this paper uses the LOG operator for edge enhancement, so the useful information is changed into straight lines and the useful feature is obvious. And the paper uses the algorithm of 2-D gray histogram to segment the image. Then it uses Hough transformation to identify the lane mark’s two edges and account its intercept and slope, then draws the midline as the final identifying result. Finally in order to reduce the count time, the paper uses the identifying results of the last frame image limit the current frame image recognition areas in tracking lane mark. The experiments results show that the lane mark can be tracking dependably and the algorithms are real-time, moreover, when the algorithm is failure, the system can also recover in time, and locks the tracking target accurately again.


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