Tool Integration for Automated Synthesis of Distributed Embedded Controllers

2022 ◽  
Vol 6 (1) ◽  
pp. 1-31
Author(s):  
Debayan Roy ◽  
Licong Zhang ◽  
Wanli Chang ◽  
Dip Goswami ◽  
Birgit Vogel-Heuser ◽  
...  
Keyword(s):  
Controller Design ◽  
Design Flow ◽  
Design Tools ◽  
Modeling And Analysis ◽  
Design Metrics ◽  
Testing And Debugging ◽  
Quality Of Control ◽  
Control Units ◽  
Software Implementations ◽  
Design Options

Controller design and their software implementations are usually done in isolated design spaces using respective COTS design tools. However, this separation of concerns can lead to long debugging and integration phases. This is because assumptions made about the implementation platform during the design phase—e.g., related to timing—might not hold in practice, thereby leading to unacceptable control performance. In order to address this, several control/architecture co-design techniques have been proposed in the literature. However, their adoption in practice has been hampered by the lack of design flows using commercial tools. To the best of our knowledge, this is the first article that implements such a co-design method using commercially available design tools in an automotive setting, with the aim of minimally disrupting existing design flows practiced in the industry. The goal of such co-design is to jointly determine controller and platform parameters in order to avoid any design-implementation gap , thereby minimizing implementation time testing and debugging. Our setting involves distributed implementations of control algorithms on automotive electronic control units ( ECUs ) communicating via a FlexRay bus. The co-design and the associated toolchain Co-Flex jointly determines controller and FlexRay parameters (that impact signal delays) in order to optimize specified design metrics. Co-Flex seamlessly integrates the modeling and analysis of control systems in MATLAB/Simulink with platform modeling and configuration in SIMTOOLS/SIMTARGET that is used for configuring FlexRay bus parameters. It automates the generation of multiple Pareto-optimal design options with respect to the quality of control and the resource usage, that an engineer can choose from. In this article, we outline a step-by-step software development process based on Co-Flex tools for distributed control applications. While our exposition is automotive specific, this design flow can easily be extended to other domains.

Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements

2021 ◽  
Vol 26 (5) ◽  
pp. 1-25
Author(s):  
Heechun Park ◽  
Bon Woong Ku ◽  
Kyungwook Chang ◽  
Da Eun Shim ◽  
Sung Kyu Lim
Keyword(s):  
State Of The Art ◽  
Physical Design ◽  
Design Flow ◽  
Design Tools ◽  
Mixed Design ◽  
Power Performance ◽  
3D Design ◽  
Qualitative And Quantitative ◽  
3D Ics ◽  
Power Delay Product

Studies have shown that monolithic 3D ( M3D ) ICs outperform the existing through-silicon-via ( TSV ) -based 3D ICs in terms of power, performance, and area ( PPA ) metrics, primarily due to the orders of magnitude denser vertical interconnections offered by the nano-scale monolithic inter-tier vias. In order to facilitate faster industry adoption of the M3D technologies, physical design tools and methodologies are essential. Recent academic efforts in developing an EDA algorithm for 3D ICs, mainly targeting placement using TSVs, are inadequate to provide commercial-quality GDS layouts. Lately, pseudo-3D approaches have been devised, which utilize commercial 2D IC EDA engines with tricks that help them operate as an efficient 3D IC CAD tool. In this article, we provide thorough discussions and fair comparisons (both qualitative and quantitative) of the state-of-the-art pseudo-3D design flows, with analysis of limitations in each design flow and solutions to improve their PPA metrics. Moreover, we suggest a hybrid pseudo-3D design flow that achieves both benefits. Our enhancements and the inter-mixed design flow, provide up to an additional 26% wirelength, 10% power consumption, and 23% of power-delay-product improvements.

scholarly journals A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime

2009 ◽  
Vol 2009 ◽  
pp. 1-10 ◽  
Author(s):  
Thilo Pionteck ◽  
Roman Koch ◽  
Carsten Albrecht ◽  
Erik Maehle
Keyword(s):  
System Architecture ◽  
Design Tool ◽  
Design Flow ◽  
Design Tools ◽  
System Architectures ◽  
Flexible System ◽  
Reconfigurable System ◽  
Communication Needs ◽  
On Chip ◽  
Architecture And Design

Runtime reconfigurable system-on-chip designs for FPGAs pose manifold demands on the underlying system architecture and design tool capabilities. The system architecture has to support varying communication needs of a changing number of processing units mapped onto diverse locations. Design tools should support an arbitrary placement of processing modules and the adjustment of boundaries of reconfigurable regions to the size of the actually instantiated processing modules. While few works address the design of flexible system architectures, the adjustment of boundaries of reconfigurable regions to the size of the actually instantiated processing modules is hardly ever considered due to design tool limitations. In this paper, a technique for circumventing this restriction is presented. It allows for a rededication of the reconfigurable area to a different number of individually sized reconfigurable regions. This technique is embedded in the design flow of a runtime reconfigurable system architecture for Xilinx Virtex-4 FPGAs. The system architecture will also be presented to provide a realistic application example.

Early Model-Based Design and Verification of Automotive Control System Software Implementations

2014 ◽  
Vol 137 (2) ◽  
Author(s):  
Mahdi Shahbakhti ◽  
Mohammad Reza Amini ◽  
Jimmy Li ◽  
Satoshi Asami ◽  
J. Karl Hedrick
Keyword(s):  
Controller Design ◽  
Combustion Engine ◽  
Control Unit ◽  
Cold Start ◽  
Early Model ◽  
Automotive Control ◽  
Model Based ◽  
Numerical Noise ◽  
Software Implementations ◽  
Hc Emissions

Verification and validation (V&V) are essential stages in the design cycle of automotive controllers to remove the gap between the designed and implemented controller. In this paper, an early model-based methodology is proposed to reduce the V&V time and improve the robustness of the designed controllers. The application of the proposed methodology is demonstrated on a cold start emission control problem in a midsize passenger car. A nonlinear reduced order model-based controller based on singular perturbation approximation (SPA) is designed to reduce cold start hydrocarbon (HC) emissions from a spark ignition (SI) combustion engine. A model-based simulation platform is created to verify the controller robustness against sampling, quantization, and fixed-point arithmetic imprecision. In addition, the results from early model-based verification are used to identify and remove sources of errors causing propagation of numerical imprecision in the controller structure. Thus the structure of the controller is modified to avoid or to reduce the level of numerical noise in the controller design. The performance of the final modified controller is validated in real-time by testing the control algorithm on a real engine control unit. The validation results indicate the modified controller is 17–63% more robust to different implementation imprecision while it requires lower implementation cost. The proposed methodology from this paper is expected to reduce typical V&V efforts in the development of automotive controllers.

scholarly journals Development, Kinematic Modeling and Analysis of 3 (DoF) Pneumatic Gantry Robot

2020 ◽  
Vol 5 (6) ◽  
pp. 646-650
Author(s):  
Awad Eisa G. Mohamed ◽  
Abuobeida Mohammed Elhassan
Keyword(s):  
Controller Design ◽  
Low Cost ◽  
Weight Ratio ◽  
Friction Model ◽  
Pneumatic Cylinder ◽  
Kinematic Modeling ◽  
Low Friction ◽  
Modeling And Analysis ◽  
Gantry Robot ◽  
Pneumatic Cylinders

Low friction pneumatic cylinders are now being considered in applications for which only electric motors or hydraulics were previously considered suitable. One potential application of low friction pneumatics is robotic for metallurgical operations where the high power to weight ratio and low cost could be exploited. As part of an ongoing project to develop a pneumatic robot, this paper presents the kinematic analysis of pneumatic cylinder characteristics that simplifies controller design. Using mathematical modeling and simulation, non-linearity of modern pneumatic systems have been investigated. The derived models give an excellent representation of the system, despite the inclusion of a simplified friction model.

scholarly journals A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era

2019 ◽  
Vol 9 (1) ◽  
pp. 9 ◽  
Author(s):  
Giovanni Scotti ◽  
Davide Zoni
Keyword(s):  
Autonomous Driving ◽  
Design Guidelines ◽  
Design Flow ◽  
Application Domain ◽  
Design Metrics ◽  
Systems On Chip ◽  
Reference Design ◽  
And Performance ◽  
On Chip ◽  
Ip Blocks

The Internet-of-Things (IoT) revolution has shaped a new application domain where low-power RISC architectures constitute the standard computational backbone. The current de-facto design practice for such architectures is to extend the ISA and the corresponding microarchitecture with custom instructions to efficiently manage the complex tasks imposed by IoT applications, i.e., augmented reality, artificial intelligence and autonomous driving, within narrow energy and area budgets. However, the new IoT application domain also offers a unique opportunity to revisit and optimize the RISC microarchitectural design flow from a more communication- and memory-centric viewpoint. This manuscript critically explores and optimizes the design of a RISC CPU front-end for IoT delivering a two-fold objective: (i) provide an optimized CPU microarchitecture; and (ii) present a set of three design guidelines to steer the implementation of IoT CPUs. The exploration sits on a newly proposed Systems-on-Chip (SoC) and RISC CPU implementing the RISC-V/IMF ISA and accounting for area, timing, and performance design metrics. Such SoC offers a reference design to evaluate pros and cons of different microarchitectural solutions. A wide combination of microarchitectures considering different branch prediction schemes, cache design architectures and on-chip bus solutions have been evaluated. The entire exploration is focused on the FPGA-based implementation due to the renewed interest for this technology demonstrated by both the research community and companies. We note that ARM launched the DesignStart FPGA program to make available the Cortex-M microcontrollers on Xilinx FPGAs in the form of IP blocks.

CONTROL OF THE CHUA'S SYSTEM BASED ON A DIFFERENTIAL FLATNESS APPROACH

2004 ◽  
Vol 14 (03) ◽  
pp. 1059-1069 ◽  
Author(s):  
CARLOS AGUILAR-IBÁÑEZ ◽  
MIGUEL SUÁREZ-CASTAÑÓN ◽  
HEBERTT SIRA-RAMÍREZ
Keyword(s):  
Trajectory Tracking ◽  
Controller Design ◽  
Pole Placement ◽  
Differential Flatness ◽  
Tracking Problem ◽  
Chaotic Circuit ◽  
Set Point ◽  
Control Approach ◽  
Additional Input ◽  
Design Options

In this paper, we present a flatness based control approach for the stabilization and tracking problem, for the well-known Chua chaotic circuit, that includes an additional input. We introduce two feedback controller design options for the set-point stabilization and the trajectory tracking problem: a direct pole placement approach, and Generalized Proportional Integral (GPI) approach based only on measured inputs and outputs.

Standard Cell-Based Low Power Embedded Controller Design

2015 ◽  
Vol 24 (06) ◽  
pp. 1550077
Author(s):  
Borisav Jovanović ◽  
Milunka Damnjanović ◽  
Predrag Petković ◽  
Vančo Litovski
Keyword(s):  
Low Power ◽  
Controller Design ◽  
Design Flow ◽  
Standard Cell ◽  
Technology Scaling ◽  
Cell Library ◽  
Ip Blocks ◽  
Comparison Of The Results ◽  
Impact Of Technology ◽  
The Impact

Microcontrollers represent unavoidable parts of state-of-the-art system-on-chips (SoCs) and they are widely embedded as IP blocks. This paper describes design steps and the application of available low-power techniques, to the design of a microcontroller IP core with 8051 instruction set, based on a prescribed standard cell libraries. Choice of the technology node and the cell library supplier is a design challenge that was considered and conclusions reached. The necessary steps of microcontroller design flow are presented which enable power reduction at several abstraction levels. An optimal microcontroller was designed to be embedded in various SoCs. The goal was to get energy-efficient microcontroller operation in applications which don't require intensive data processing. The impact of technology scaling on microcontroller energy efficiency is considered by comparison of the results obtained from implementations in three standard cell technologies. Moreover, power dissipation models are created which allow for microcontroller's power estimation in low throughput sensors networks applications.

Design Flow and Design Tools

2018 ◽  
pp. 87-115
Author(s):  
Tomonori Izumi ◽  
Yukio Mitsuyama
Keyword(s):  
Design Flow ◽  
Design Tools

scholarly journals Avr System Analysis and Simulation by Using Fopid and Parameters Variation Effects

2021 ◽  
Vol 309 ◽  
pp. 01033
Author(s):  
Choppadandi Srikanth ◽  
Dola Gobinda Padhan ◽  
N. Kiran Kumar
Keyword(s):  
System Analysis ◽  
Reactive Power ◽  
Controller Design ◽  
Space Technology ◽  
Parameter Uncertainties ◽  
Voltage Level ◽  
Response Characteristics ◽  
Control Units ◽  
Avr System ◽  
Fractional Filter

The FOPID control units for an AVR system with a fractional filter are a unique fractional order. The main responsibility for controlling the reactive power and voltage level is an automated tensile regulator (AVR). PID controller, sensor, exciter, and stabiliser or amplifier are used for the module system. The system is designed according to state-space technology. The proposed controller must have seven independent parameters. A comparison of the published study with optimal adjusted AVR PID and FOPID controls also shows that the proposed controller is superior. The recommended controls derived from the bode analysis with their frequency response characteristics are shown. Finally, the resilience of the controller design is individually examined for both the parameter uncertainties of AVR system and outside storages introduced into AVR system. Given the overall results presented there are clear improvements to the performance of AVR system by a fractional filter in a proposed FOPID controller, and that the AVR system may successfully be applied to the suggested control.

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