A 3.3-V 12b 50-MS/s A/D Converter in 0.6-µm CMOS with over 80-dB SFDR

Analog Circuit Design ◽

10.1007/978-1-4757-3198-9_3 ◽

2000 ◽

pp. 47-73 ◽

Cited By ~ 1

Author(s):

Hui Pan ◽

Masahiro Segami ◽

Michael Choi ◽

Jing Cao ◽

Fumitoshi Hatori ◽

...

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