Verifying VHDL Designs with Multiple Clocks in SMV

Formal Methods: Applications and Technology - Lecture Notes in Computer Science ◽

10.1007/978-3-540-70952-7_10 ◽

2007 ◽

pp. 148-164

Author(s):

A. Smrčka ◽

V. Řehák ◽

T. Vojnar ◽

D. Šafránek ◽

P. Matoušek ◽

...

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