An improved approach for marking optimization of timed weighted
marked graphs

In this paper, we introduce a notion of virtual marked graphs and their equivalence and then define polynomial invariants for virtual marked graphs using invariants for virtual links. We also formulate a way how to define the ideal coset invariants for virtual surface-links using the polynomial invariants for virtual marked graphs. Examining this theory with the Kauffman bracket polynomial, we establish a natural extension of the Kauffman bracket polynomial to virtual marked graphs and found the ideal coset invariant for virtual surface-links using the extended Kauffman bracket polynomial.

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Parametric transformation of timed weighted marked graphs: applications in optimal resource allocation

IEEE/CAA Journal of Automatica Sinica ◽

10.1109/jas.2020.1003477 ◽

2021 ◽

Vol 8 (1) ◽

pp. 179-188

Author(s):

Zhou He ◽

Ziyue Ma ◽

Zhiwu Li ◽

Alessandro Giua

Keyword(s):

Resource Allocation ◽

Optimal Resource Allocation ◽

Marked Graphs ◽

Optimal Resource ◽

Parametric Transformation

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Scheduling Timed Marked Graphs with Resources: A Serial Method

IFAC Proceedings Volumes ◽

10.1016/s1474-6670(17)40592-1 ◽

1998 ◽

Vol 31 (15) ◽

pp. 439-444 ◽

Cited By ~ 1

Author(s):

Pascal Richard

Keyword(s):

Marked Graphs

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Proper Augmented Marked Graphs

Augmented Marked Graphs ◽

10.1007/978-3-319-06428-4_4 ◽

2014 ◽

pp. 55-66 ◽

Cited By ~ 1

Author(s):

King Sing Cheung

Keyword(s):

Marked Graphs

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Augmented Marked Graphs

Augmented Marked Graphs ◽

10.1007/978-3-319-06428-4_3 ◽

2014 ◽

pp. 33-53

Author(s):

King Sing Cheung

Keyword(s):

Marked Graphs

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Buffer Placement and Sizing for High-Performance Dataflow Circuits

ACM Transactions on Reconfigurable Technology and Systems ◽

10.1145/3477053 ◽

2022 ◽

Vol 15 (1) ◽

pp. 1-32

Author(s):

Lana Josipović ◽

Shabnam Sheikhha ◽

Andrea Guerrieri ◽

Paolo Ienne ◽

Jordi Cortadella

Keyword(s):

Performance Optimization ◽

Optimization Model ◽

High Performance ◽

Control Flow ◽

High Level Synthesis ◽

Software Applications ◽

Marked Graphs ◽

Variable Latency ◽

High Level ◽

Strong Contrast

Commercial high-level synthesis tools typically produce statically scheduled circuits. Yet, effective C-to-circuit conversion of arbitrary software applications calls for dataflow circuits, as they can handle efficiently variable latencies (e.g., caches), unpredictable memory dependencies, and irregular control flow. Dataflow circuits exhibit an unconventional property: registers (usually referred to as “buffers”) can be placed anywhere in the circuit without changing its semantics, in strong contrast to what happens in traditional datapaths. Yet, although functionally irrelevant, this placement has a significant impact on the circuit’s timing and throughput. In this work, we show how to strategically place buffers into a dataflow circuit to optimize its performance. Our approach extracts a set of choice-free critical loops from arbitrary dataflow circuits and relies on the theory of marked graphs to optimize the buffer placement and sizing. Our performance optimization model supports important high-level synthesis features such as pipelined computational units, units with variable latency and throughput, and if-conversion. We demonstrate the performance benefits of our approach on a set of dataflow circuits obtained from imperative code.

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