On the Dynamic Logic of Agency and Action

Chrysafis Hartonas

doi:10.1007/s11225-013-9473-8

On the Dynamic Logic of Agency and Action

Studia Logica ◽

10.1007/s11225-013-9473-8 ◽

2013 ◽

Vol 102 (3) ◽

pp. 441-478 ◽

Cited By ~ 1

Author(s):

Chrysafis Hartonas

Keyword(s):

Dynamic Logic ◽

Logic Of Agency

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A Dynamic Logic of Agency II: Deterministic $${\mathcal{DLA}}$$ , Coalition Logic, and Game Theory

Journal of Logic Language and Information ◽

10.1007/s10849-009-9104-y ◽

2009 ◽

Vol 19 (3) ◽

pp. 327-351 ◽

Cited By ~ 10

Author(s):

Emiliano Lorini

Keyword(s):

Game Theory ◽

Dynamic Logic ◽

Coalition Logic ◽

Logic Of Agency

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A Computationally Grounded Dynamic Logic of Agency, with an Application to Legal Actions

Lecture Notes in Computer Science - Deontic Logic in Computer Science ◽

10.1007/978-3-642-31570-1_12 ◽

2012 ◽

pp. 170-183

Author(s):

Andreas Herzig ◽

Tiago de Lima ◽

Emiliano Lorini ◽

Nicolas Troquard

Keyword(s):

Dynamic Logic ◽

Logic Of Agency

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A Dynamic Logic of Agency I: STIT, Capabilities and Powers

Journal of Logic Language and Information ◽

10.1007/s10849-009-9105-x ◽

2009 ◽

Vol 19 (1) ◽

pp. 89-121 ◽

Cited By ~ 18

Author(s):

Andreas Herzig ◽

Emiliano Lorini

Keyword(s):

Dynamic Logic ◽

Logic Of Agency

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Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs

International Journal of Sensors Wireless Communications and Control ◽

10.2174/2210327909666190207163639 ◽

2020 ◽

Vol 10 (1) ◽

pp. 55-62

Author(s):

Deepika Bansal ◽

Bal Chand Nagar ◽

Brahamdeo Prasad Singh ◽

Ajay Kumar

Keyword(s):

Power Consumption ◽

High Performance ◽

Dynamic Logic ◽

Clock Frequency ◽

Charge Sharing ◽

Benchmark Circuit ◽

Domino Circuit ◽

Power Delay Product ◽

Domino Circuits ◽

Or Gate

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.

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