A comprehensive survey of network coding in vehicular ad-hoc networks

2016 ◽  
Vol 23 (8) ◽  
pp. 2395-2414 ◽  
Author(s):  
Farhan Jamil ◽  
Anam Javaid ◽  
Tariq Umer ◽  
Mubashir Husain Rehmani
2021 ◽  
Vol 12 (4) ◽  
pp. 1-30
Author(s):  
Zhenchang Xia ◽  
Jia Wu ◽  
Libing Wu ◽  
Yanjiao Chen ◽  
Jian Yang ◽  
...  

Vehicular ad hoc networks ( VANETs ) and the services they support are an essential part of intelligent transportation. Through physical technologies, applications, protocols, and standards, they help to ensure traffic moves efficiently and vehicles operate safely. This article surveys the current state of play in VANETs development. The summarized and classified include the key technologies critical to the field, the resource-management and safety applications needed for smooth operations, the communications and data transmission protocols that support networking, and the theoretical and environmental constructs underpinning research and development, such as graph neural networks and the Internet of Things. Additionally, we identify and discuss several challenges facing VANETs, including poor safety, poor reliability, non-uniform standards, and low intelligence levels. Finally, we touch on hot technologies and techniques, such as reinforcement learning and 5G communications, to provide an outlook for the future of intelligent transportation systems.


2020 ◽  
Vol 2020 ◽  
pp. 1-14 ◽  
Author(s):  
Shujuan Wang ◽  
Qian Zhang ◽  
Shuguang Lu

Vehicular Ad hoc NETworks (VANETs) are becoming an important part of people’s daily life, as they support a wild range of applications and have great potential in critical fields such as accident warning, traffic control and management, infotainment, and value-added services. However, the harsh and stringent transmission environment in VANETs poses a great challenge to the efficient and effective data dissemination for VANETs, which is the essential in supporting and providing the desired applications. To resolve this issue, Instantly Decodable Network Coding (IDNC) technology is applied to stand up to the tough transmission conditions and to advance the performance. This paper proposes a novel admission control method that works well with any IDNC-assisted data dissemination algorithm, to achieve fast and reliable data dissemination in VANETs. Firstly, the proposed admission control strategy classifies the safety-related applications as high priority and the user-related applications as low priority. It then conducts different admission policies on these two prioritized applications’ data. An artfully designed network coding-aware admission policy is proposed to regulate the flow of low-priority data requests and to prevent the network from congestion, through comparing the vectorized distances between the data requests and the encoding packets. Moreover, the carefully planned admission strategy is benefit for maximizing the network coding opportunities by inclining to admit requests which can contribute more to the encoding clique, thus further enhancing the system performance. Simulation results approve that the proposed admission control method achieves clear advantages in terms of delay, deadline miss ratio, and download success ratio.


2012 ◽  
Vol 8 (1) ◽  
pp. 45-59 ◽  
Author(s):  
Sunwoo Kim ◽  
Won W. Ro

Network coding is a promising technique for data communications in wired and wireless networks. However, it places an additional computing overhead on the receiving node in exchange for the improved bandwidth. This paper proposes an FPGA-based reconfigurable and parallelized network coding decoder for embedded systems especially for vehicular ad hoc networks. In our design, rapid decoding process can be achieved by exploiting parallelism in the coefficient vector operations. The proposed decoder is implemented by using a modern Xilinx Virtex-5 device and its performance is evaluated considering the performance of the software decoding on various embedded processors. The performance on four different sizes of the coefficient matrix is measured and the decoding throughput of 18.3 Mbps for the size 16 × 16 and 6.5 Mbps for 128 × 128 has been achieved at the operating frequency of 64.5 MHz. Compared to the recent TEGRA 250 processor, the result obtained with128 × 128 coefficient matrix reaches up to 5.06 in terms of speedup.


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