High Slew-Rate and Very-Low Output Resistance Class-AB Flipped Voltage Follower Cell for Low-Voltage Low-Power Analog Circuits

2021 ◽  
Author(s):  
Caffey Jindal ◽  
Rishikesh Pandey
Keyword(s):  
Low Power ◽  
Analog Circuits ◽  
Low Voltage ◽  
Slew Rate ◽  
Output Resistance ◽  
Class Ab ◽  
Flipped Voltage Follower ◽  
Voltage Follower

Design of CNTFET-Based CCII Using gm/ID Technique for Low-Voltage and Low-Power Applications

2019 ◽  
Vol 29 (09) ◽  
pp. 2050143 ◽  
Author(s):  
Mohd Yasir ◽  
Naushad Alam
Keyword(s):  
Carbon Nanotube ◽  
Low Power ◽  
Analog Circuits ◽  
Low Voltage ◽  
Drain Current ◽  
Current Gain ◽  
Class Ab ◽  
Op Amp ◽  
Analog Ic ◽  
The Difference

This paper introduces for the first time all the steps required in the optimal design of carbon nanotube field-effect transistor (CNTFET)-based second generation current conveyor (CCII) using transconductance-to-drain current ratio ([Formula: see text]) technique for low-voltage (LV) and low-power (LP) applications. The [Formula: see text] technique is a well-established methodology for CMOS analog IC design. However, the difference between CMOS and CNTFET is that CMOS has continuous width while the width of CNTFET is discrete and depends on different parameters like the number of tubes, pitch and diameter ([Formula: see text]) of the carbon nanotube (CNT). Therefore, there is a need for a design technique by which one can easily design analog circuits using CNTFETs. The CCII is based on two-stage op-amp and two inverters used as class AB amplifiers. The performance of CCII has been extensively examined in terms of DC, AC and transient responses of node voltages, branch currents and node impedances using HSPICE simulations. The CCII operates at [Formula: see text]0.5[Formula: see text]V and has 172[Formula: see text][Formula: see text]W of power consumption. The designed CCII provides very high 3-dB bandwidth (BW) for current gain ([Formula: see text][Formula: see text]GHz as well as voltage gain ([Formula: see text][Formula: see text]GHz.

A Class-AB Bulk-Driven Amplifier with Enhanced Transconductance Using Quasi-Floating Gate Method

2018 ◽  
Vol 27 (09) ◽  
pp. 1850137
Author(s):  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
Cmos Technology ◽  
Floating Gate ◽  
Common Source ◽  
Slew Rate ◽  
Power Budget ◽  
Ultra Low Power ◽  
Class Ab ◽  
Flipped Voltage Follower ◽  
Voltage Follower ◽  
Adaptive Biasing

This paper presents a supper class-AB adaptive biasing bulk-driven amplifier for ultra-low-power applications. In the proposed structure, two bulk-driven flipped voltage follower (FVF) cells are reconfigured as nonlinear tail currents using quasi-floating gate method to enhance transconductance and slew rate. In addition, two idle current controllers are employed as common source amplifiers to provide a supper class-AB structure without increasing total current consumption. The proposed structure is simulated in 0.18-[Formula: see text]m CMOS technology at 0.5[Formula: see text]V supply with 35[Formula: see text]nW power budget. The results show a 57.9[Formula: see text]dB DC gain, 8.8[Formula: see text]kHz gain bandwidth and 38.2[Formula: see text]V/ms slew rate for the proposed amplifier.

scholarly journals Class AB flipped voltage follower with very low output resistance and no additional power

2018 ◽  
Vol 15 (4) ◽  
pp. 20171170-20171170 ◽  
Author(s):  
Ivan Padilla-Cantoya ◽  
Jesus E. Molinar-Solis ◽  
Jaime Ramirez-Angulo
Keyword(s):  
Output Resistance ◽  
Class Ab ◽  
Flipped Voltage Follower ◽  
Voltage Follower

High Performance CMOS Current Mirror Using Class-AB Level Shifted Bulk Driven Flipped Voltage Follower Cell

2019 ◽  
Vol 28 (08) ◽  
pp. 1950140
Author(s):  
Caffey ◽  
Rishikesh Pandey
Keyword(s):  
Supply Voltage ◽  
Tracking Error ◽  
Cmos Technology ◽  
Current Mirror ◽  
Design Environment ◽  
Output Resistance ◽  
Class Ab ◽  
Flipped Voltage Follower ◽  
Voltage Follower ◽  
High Output

This paper presents a novel current mirror structure based on level shifted class-AB flipped voltage follower cell, which operates at the supply voltage of 1.2[Formula: see text]V. The level shifted class-AB flipped voltage follower cell and regulated cascode structure are used at the input and the output stages to achieve low input resistance and very high output resistance, respectively. A comparison of performance parameters of the proposed current mirror with existing structures shows that the proposed current mirror has a very less current tracking error of 0.99%, high output resistance of 18.7[Formula: see text]M[Formula: see text], wide bandwidth of 239.245[Formula: see text]MHz and low power dissipation of 104[Formula: see text][Formula: see text]W. The proposed circuit has been simulated in Cadence virtuoso analog design environment and layout of the proposed circuit has been designed in Cadence virtuoso layout XL editor using BSIM3V3 180[Formula: see text]nm CMOS technology. The post-layout simulation results have also been presented to demonstrate the effectiveness of the proposed circuit.

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