Carrier separation analysis for clarifying carrier conduction and degradation mechanisms in high-k stack gate dielectrics

2005 ◽  
Vol 45 (7-8) ◽  
pp. 1041-1050 ◽  
Author(s):  
Wataru Mizubayashi ◽  
Naoki Yasuda ◽  
Kenji Okada ◽  
Hiroyuki Ota ◽  
Hirokazu Hisamatsu ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Degradation Mechanisms ◽  
High K ◽  
Carrier Separation

High K gate dielectrics for the silicon industry

2002 ◽  
Author(s):  
L. Manchanda ◽  
B. Busch ◽  
M.L. Green ◽  
M. Morris ◽  
R.B. van Dover ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
High K

Strategic Customization of Polymeric Nanocomposites Modified by 2D Titanium Oxide Nanosheet for High‐ k and Flexible Gate Dielectrics

Small ◽  
2021 ◽  
Vol 17 (17) ◽  
pp. 2007213
Author(s):  
Moonjeong Jang ◽  
Se Yeon Park ◽  
Seong Ku Kim ◽  
Dowon Jung ◽  
Wooseok Song ◽  
...  
Keyword(s):  
Titanium Oxide ◽  
Gate Dielectrics ◽  
Polymeric Nanocomposites ◽  
High K

Process and Manufacturing Challenges for High-K Gate Stack Systems

1999 ◽  
Vol 567 ◽  
Author(s):  
M.C. Gilmer ◽  
T-Y Luo ◽  
H.R. Huff ◽  
M.D. Jackson ◽  
S. Kim ◽  
...  
Keyword(s):  
Silicon Surface ◽  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Metal Electrode ◽  
Significant Variable ◽  
Tem Analysis ◽  
Physical Mechanisms ◽  
High K ◽  
Commercial Equipment

ABSTRACTA design-of-experiments methodology was implemented to assess the commercial equipment viability to fabricate the high-K dielectrics Ta2O5, TiO2 and BST (70/30 and 50/50 compositions) for use as gate dielectrics. The high-K dielectrics were annealed in 100% or 10% O2 for different times and temperatures in conjunction with a previously prepared NH3 nitrided or 14N implanted silicon surface. Five metal electrode configurations—Ta, TaN, W, WN and TiN—were concurrently examined. Three additional silicon surface configurations were explored in conjunction with a more in-depth set of time and temperature anneals for Ta2O5. Electrical characterization of capacitors fabricated with the above high-K gate dielectrics, as well as SIMS and TEM analysis, indicate that the post high-K deposition annealing temperature was the most significant variable impacting the leakage current density, although there was minimal influence on the capacitance. Further studies are required, however, to clarify the physical mechanisms underlying the electrical data presented.

Bonding Constraints at Interfaces Between Crystalline Si and Stacked Gate Dielectrics

1999 ◽  
Vol 567 ◽  
Author(s):  
G. Lucovsky ◽  
J.C. Phillips
Keyword(s):  
Metal Oxides ◽  
Transition Metal Oxides ◽  
Chemical Bonding ◽  
Gate Dielectrics ◽  
Nuclear Charge ◽  
Dielectric Materials ◽  
Band Offset ◽  
High K ◽  
Dielectric Interfaces ◽  
Mechanical Bonding

ABSTRACTThis paper discusses chemical bonding effects at Si-dielectric interfaces that are important in the implementation of alternative gate dielectrics including: i) the character of interfacial bonds, either isovalent with bond and nuclear charge balanced as in Si-SiO2, or heterovalent, with an inherent mismatch between bond and nuclear charge, ii) mechanical bonding constraints related to the average number of bonds/atom, Nay, and iii) band offset energies that are reduced in transition metal oxides due to the d-state origins of the conduction band states. Applications are made to specific classes of dielectric materials including i) nitrides and oxide/nitride stacks and ii) alternative high-K gate materials.

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