scholarly journals Characterization of large tsunamigenic landslides and their effects using digital surface models: A case study from Taan Fiord, Alaska

2022 ◽  
Vol 270 ◽  
pp. 112881
Author(s):  
Brianna D. Corsa ◽  
Mylène Jacquemart ◽  
Michael J. Willis ◽  
Kristy F. Tiampo
Keyword(s):  
Author(s):  
D. L. Callahan

Modern polishing, precision machining and microindentation techniques allow the processing and mechanical characterization of ceramics at nanometric scales and within entirely plastic deformation regimes. The mechanical response of most ceramics to such highly constrained contact is not predictable from macroscopic properties and the microstructural deformation patterns have proven difficult to characterize by the application of any individual technique. In this study, TEM techniques of contrast analysis and CBED are combined with stereographic analysis to construct a three-dimensional microstructure deformation map of the surface of a perfectly plastic microindentation on macroscopically brittle aluminum nitride.The bright field image in Figure 1 shows a lg Vickers microindentation contained within a single AlN grain far from any boundaries. High densities of dislocations are evident, particularly near facet edges but are not individually resolvable. The prominent bend contours also indicate the severity of plastic deformation. Figure 2 is a selected area diffraction pattern covering the entire indentation area.


2011 ◽  
Author(s):  
Giorgio Rocco Cavanna ◽  
Ernesto Caselgrandi ◽  
Elisa Corti ◽  
Alessandro Amato del Monte ◽  
Massimo Fervari ◽  
...  

Author(s):  
Amy Poe ◽  
Steve Brockett ◽  
Tony Rubalcava

Abstract The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.


Author(s):  
Sweta Pendyala ◽  
Dave Albert ◽  
Katherine Hawkins ◽  
Michael Tenney

Abstract Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.


Author(s):  
Martin Versen ◽  
Dorina Diaconescu ◽  
Jerome Touzel

Abstract The characterization of failure modes of DRAM is often straight forward if array related hard failures with specific addresses for localization are concerned. The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM periphery. The failure mode analysis and fault modeling focus both on the root-cause and on the test aspects of the problem.


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