Defect reduction in oxygen implanted silicon-on-insulator material during high-temperature annealing

1989 ◽  
Vol 47 ◽  
pp. 604-605
Author(s):  
P. Roitman ◽  
B. Cordts ◽  
S. Visitserngtrakul ◽  
S.J. Krause
Keyword(s):  
High Temperature ◽  
Annealing Temperature ◽  
Silicon On Insulator ◽  
High Dose ◽  
High Temperature Annealing ◽  
High Current ◽  
Defect Reduction ◽  
Annealing Step ◽  
Multiple Cycle ◽  
Defect Densities

Synthesis of a thin, buried dielectric layer to form a silicon-on-insulator (SOI) material by high dose oxygen implantation (SIMOX – Separation by IMplanted Oxygen) is becoming an important technology due to the advent of high current (200 mA) oxygen implanters. Recently, reductions in defect densities from 109 cm−2 down to 107 cm−2 or less have been reported. They were achieved with a final high temperature annealing step (1300°C – 1400°C) in conjunction with: a) high temperature implantation or; b) channeling implantation or; c) multiple cycle implantation. However, the processes and conditions for reduction and elimination of precipitates and defects during high temperature annealing are not well understood. In this work we have studied the effect of annealing temperature on defect and precipitate reduction for SIMOX samples which were processed first with high temperature, high current implantation followed by high temperature annealing.

Effect of temperature on defect formation during oxygen implantation of silicon-on-insulator material

1990 ◽  
Vol 48 (4) ◽  
pp. 578-579
Author(s):  
C. O. Jung ◽  
S. Visitsemgtrakul ◽  
S.J. Krause ◽  
P. Roitman ◽  
B. Cordts
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Defect Structure ◽  
Defect Formation ◽  
Silicon On Insulator ◽  
Effect Of Temperature ◽  
Implantation Temperature ◽  
Annealing Step ◽  
Multiple Cycle ◽  
Defect Densities

Oxygen implanted silicon-on-insulator material, SIMOX, (Separation by IMplanted Oxygen) provides improved speed and radiation hardness over bulk silicon for integrated circuits which are built on the thin superficial Si layer above the buried oxide layer. A high quality superficial Si layer is required, but may be degraded by high defect densities of 109 to 1010 cm-2 in annealed SIMOX. Defect densities have been reduced down to 106cm-2 or less. They were achieved with a final high temperature annealing step (1300-1400°C) in conjunction with: a) high temperature implantation or; b) channeling implantation or; c) multiple cycle implantation. The defect structure developed during implantation, which is strongly affected by temperature, plays a significant role in the defect structure in the annealed material. In this work we are reporting on the effect of implantation temperature on defect formation and also some new details on the structure of the defects that are present.

High-Quality SOI by Oxygen Implantation into Silicon

1987 ◽  
Vol 93 ◽  
Author(s):  
A. H. van Ommen ◽  
H. J. Ligthart ◽  
J. Politiek ◽  
M. P. A. Viegers
Keyword(s):  
High Temperature ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
High Dose ◽  
High Temperature Annealing ◽  
High Quality ◽  
Cubic Symmetry ◽  
Buried Oxide ◽  
Simple Cubic ◽  
Precipitate Growth

ABSTRACTHigh quality Silicon-On-Insulator, with a dislocation density lower than 105cm−2, has been formed by high temperature annealing of high-dose oxygen implanted silicon. In the as-implanted state, oxygen was found to form precipitates in the top silicon film. In the upper region these precipitates were found to order into a superlattice of simple cubic symmetry. Near the interface with the buried oxide film the precipitates are larger and no ordering occurs in that region. Contrary to implants without precipitate ordering where dislocations are observed across the entire layer thickness of the top silicon film, dislocations are now only found near the buried oxide. The precipitate ordering appears to prevent the dislocations to climb to the surface. High temperature annealing results in precipitate growth in this region whereas they dissolve elsewhere. These growing precipitates pin the dislocations and elimination of precipitates and dislocations occurs simultaneously, resulting in good quality SOI material.

Precipitation in silicon-on-insulator material during high- temperature annealing

1987 ◽  
Vol 45 ◽  
pp. 254-255
Author(s):  
S. J. Krause ◽  
C. O. Jung ◽  
S.R. Wilson
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Annealing Time ◽  
High Speed ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Precipitate Size ◽  
High Dose ◽  
High Temperature Annealing ◽  
Implantation Energy

Silicon-on-insulator (SOI) structure by high dose oxygen implantation (SIMOX) has excellent potential for use in radiation hardened and high speed integrated circuits. Device fabrication in SIMOX requires a high quality superficial Si layer above the buried oxide layer. Previously we reported on the effect of heater temperature, background doping, and annealing cycle on precipitate size, density, and location in the superficial Si layer. Precipitates were not eliminated with our processing conditions, but various authors have recently reported that high temperature annealing of SIMOX, from 1250°C to 1405°C, eliminates virtually all precipitates in the superficial Si layer. However, in those studies there were significant differences in implantation energy and dose and also annealing time and temperature. Here we are reporting on the effect of annealing time and temperature on the formation and changes in precipitates.

Evolution and Future Trends of SIMOX Material

MRS Bulletin ◽  
1998 ◽  
Vol 23 (12) ◽  
pp. 25-29 ◽  
Author(s):  
Steve Krause ◽  
Maria Anc ◽  
Peter Roitman
Keyword(s):  
High Temperature ◽  
Low Power ◽  
High Speed ◽  
New Technologies ◽  
Low Voltage ◽  
Semiconductor Industry ◽  
High Energy ◽  
Silicon On Insulator ◽  
High Dose ◽  
High Temperature Annealing

Oxygen-implanted silicon-on-insulator (SOI) material, or SIMOX (separation by implantation of oxygen), is another chapter in the continuing development of new material technologies for use by the semiconductor industry. Building integrated circuits (ICs) in a thin layer of crystalline silicon on a layer of silicon oxide on a silicon substrate has benefits for radiationhard, high-temperature, high-speed, low-voltage, and low-power operation, and for future device designs. Historically the first interest in SIMOX was for radiation-hard electronics for space, but the major application of interest currently is low-power, high-speed, portable electronics. Silicon-on-insulator also avoids the disadvantage of a completely different substrate such as sapphire or gallium arsenide. Formation of a buried-oxide (BOX) layer by high-energy, high-dose, oxygen ion implantation has the advantage that the ion-implant dose can be made extremely precise and extremely uniform. However the silicon and oxide layers are highly damaged after the implant, so high-temperature annealing sequences are required to restore devicequality material. In fact SIMOX process development necessitated the development of new technologies for high-dose implantation and high-temperature annealing.

Silicon on Insulator by High Dose Implantation

1984 ◽  
Vol 33 ◽  
Author(s):  
P. L. F. Hemment
Keyword(s):  
Physical Properties ◽  
Thermal Processing ◽  
Vlsi Circuits ◽  
Silicon On Insulator ◽  
High Dose ◽  
High Current ◽  
Processing Technologies ◽  
Oxygen Ions ◽  
High Doses ◽  
High Dose Implantation

ABSTRACTSilicon on insulator structures consisting of a buried dielectric, formed by the implantation of high doses of oxygen ions, have been shown to be suitable substrates for LSI circuits. The substrates are compatible with present silicon processing technologies and are confidently expected to be suitable for VLSI circuits. In this paper the microstructure and physical properties of this SOI material will be described and the dependence of these characteristics upon the implantation conditions and subsequent thermal processing will be discussed. With this information, it is then possible to outline the specification for a high current oxygen implanter.

PHASE EVOLUTION AND MAGNETIC PROPERTIES OF FEPT-PTTE2 NANORODS

2009 ◽  
Vol 23 (17) ◽  
pp. 3573-3578
Author(s):  
QINGYU YAN ◽  
AIDONG LI
Keyword(s):  
Magnetic Properties ◽  
Phase Transformation ◽  
High Temperature ◽  
Annealing Temperature ◽  
Phase Evolution ◽  
Polyol Process ◽  
Phase Ratio ◽  
High Temperature Annealing ◽  
Two Phase

FePt - PtTe 2 two phase nanorods have been produced by a polyol process. The shape and magnetic properties of two phase nanorods with different phase ratio are investigated. L10 phase transformation of FePt in the nanorods has been accomplished at annealing temperature as low as 400 °C with Hc above 500mT. High temperature annealing causes the disintegration of the nanorods due the melting/evaporation of Te element.

Instabilities and Point Defects at Step-Free Si(001) and (111) Terraces During High Temperature Annealing

1999 ◽  
Vol 587 ◽  
Author(s):  
Doohan Lee ◽  
Jack M. Blakely
Keyword(s):  
High Temperature ◽  
Point Defect ◽  
Point Defects ◽  
Strain Energy ◽  
Annealing Temperature ◽  
Small Islands ◽  
High Temperature Annealing ◽  
Atomic Steps ◽  
The Stability

AbstractIn this paper we describe observations on the stability of extremely large Si(001) and (111) terraces that are formed by a technique described previously. Following annealing at high temperature and quenching, a series of concentric pits of monoatomic depth are observed with spacing between successive pits of the order of several microns; pits do not form on (111) until the terraces get extremely large. The occurrence of small islands or small pits on the terraces of quenched samples gives information on the majority point defect at the annealing temperature. On (001) samples that are slowly cooled from the annealing temperature, it is observed that pairs of atomic steps have formed on the large terrace; we believe that these result from the tendency of the surface to minimize the strain energy associated with the (2 × 1) reconstruction.

Aluminum-Ion Implantation into 4H-SiC (11-20) and (0001)

2004 ◽  
Vol 815 ◽  
Author(s):  
Y. Negoro ◽  
T. Kimoto ◽  
H. Matsunami
Keyword(s):  
High Temperature ◽  
Sheet Resistance ◽  
Room Temperature ◽  
Dose Dependence ◽  
High Dose ◽  
High Temperature Annealing ◽  
Aluminum Ion ◽  
Hall Effect Measurements ◽  
Short Time ◽  
Surface Morphologies

AbstractHigh-dose aluminum-ion (Al+) implantation into 4H-SiC (11-20) and (0001) has been investigated. Surface morphologies of implanted (0001) samples were improved by annealing with a graphite cap. Implant-dose dependence and annealing-time dependence of electrical properties are examined by Hall-effect measurements. A low sheet resistance of 2.3 kΩ/sq. was obtained in (0001) by high-dose Al+ implantation at 500 °C with a dose of 3.0 × 1016 cm−2 and high-temperature annealing at 1800 °C for a short time of 1 min. In the case of (11-20), even room-temperature implantation brought a low sheet resistance below 2 kΩ/sq. after annealing at 1800 °C.

Growth of Carbon Nanotubes on Fully Processed Silicon-On-Insulator CMOS Substrates

2008 ◽  
Vol 8 (11) ◽  
pp. 5667-5672 ◽  
Author(s):  
M. Samiul Haque ◽  
S. Zeeshan Ali ◽  
P. K. Guha ◽  
S. P. Oei ◽  
J. Park ◽  
...  
Keyword(s):  
Carbon Nanotubes ◽  
High Temperature ◽  
High Temperatures ◽  
Heat Dissipation ◽  
Thermal Conductance ◽  
Silicon On Insulator ◽  
High Current ◽  
Large Area ◽  
Growth Method ◽  
Soi Cmos

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

Ni-Based Ohmic Contacts to Silicon Carbide Examined by Electron Microscopy

2012 ◽  
Vol 186 ◽  
pp. 82-85 ◽  
Author(s):  
Marek Wzorek ◽  
Andrzej Czerwiński ◽  
Andrian V. Kuchuk ◽  
Jacek Ratajczak ◽  
Ania Piotrowska ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Silicon Carbide ◽  
High Temperature ◽  
Phase Transformations ◽  
Formation Mechanism ◽  
Ohmic Contacts ◽  
Contact Layer ◽  
Contact Structures ◽  
High Temperature Annealing ◽  
Annealing Step

Ni/Si multilayer contact structures to 4H-SiC after subsequent annealing steps are investigated with electron microscopy methods. After high temperature annealing step, specific defects in the contact structures are observed. The influence of phase transformations during annealings on the morphology on the contacts is discussed and the explanation of formation mechanism of voids within contact layer is proposed.

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