FTIR analysis of printed-circuit board residue

Author(s):  
Sharon A. Myers ◽  
Troy D. Cognata ◽  
Hugh Gotts

Logic boards were failing at Enhanced Mac Minus One (EMMO) test or Integrated Circuit Test (ICT) after printed circuit board (PCB) rework. The failure to boot was originally traced to a suspected bad microcontroller chip. Replacing this chip, or an oscillator tied to the microcontroller circuit, did not consistently solve the boot problem. With further testing, it was found the microcontroller circuit was very sensitive to resistance and was essentially shorted.A resistor in the microcontroller circuit was identified on the flip side of the PCB. Several areas on the board, including the resistor R161, were seen to have a slight white haze/ low gloss appearance on the surface of the PCB. To test if the residue was electrically conductive, five boards were selected whose sole failure was R161. The resistance of the individual resistors was measured with a digital multimeter (DMM). The resistor was then cleaned with isopropyl alcohol and a cotton swab. Each board was retested at ICT and the individual resistors measured again with a DMM. Cleaning the area surrounding the resistor with isopropyl alcohol, corrected the failure four of the times.

Author(s):  
William Ng ◽  
Kevin Weaver ◽  
Zachary Gemmill ◽  
Herve Deslandes ◽  
Rudolf Schlangen

Abstract This paper demonstrates the use of a real time lock-in thermography (LIT) system to non-destructively characterize thermal events prior to the failing of an integrated circuit (IC) device. A case study using a packaged IC mounted on printed circuit board (PCB) is presented. The result validated the failing model by observing the thermal signature on the package. Subsequent analysis from the backside of the IC identified a hot spot in internal circuitry sensitive to varying value of external discrete component (inductor) on PCB.


Author(s):  
Arun Gowda ◽  
Anthony Primavera ◽  
K. Srihari

The implementation of lead-free solder into an electronics assembly process necessitates the reassessment of the individual factors involved in component attachment and rework. A component assembly undergoes multiple thermal cycles during rework. With the use of lead-free solder, the assemblies are subjected to higher assembly and rework temperatures than those required for eutectic tin-lead assemblies. The rework of lead-free area array components involves the removal of defective component, preparation of the printed circuit board attachment pad (site redressing), solder paste replenishment or flux deposition, and component placement and reflow. This paper primarily focuses on the site redressing aspect of lead-free rework, followed by the development of rework processes for lead-free chip scale packages utilizing the knowledge gained in the site redressing studies.


Proceedings ◽  
2019 ◽  
Vol 27 (1) ◽  
pp. 19
Author(s):  
Bushra Jalil ◽  
Bilal Hussain ◽  
Maria Pascali ◽  
Giovanni Serafino ◽  
Davide Moroni ◽  
...  

Microwave photonic systems are more susceptible to thermal fluctuations due to thermo-optic effect. In order to stabilize the performance of photonic components, thermal monitoring is achieved by using thermistors placed at any arbitrary location along the component. This work presents non contact thermography of a fully functional microwave photonic system. The temperature profile of printed circuit board (PCB) and photonic integrated circuit (PIC) is obtained using Fluke FLIR (A65) camera. We performed Otsu’s thresholding to segment heat centers located across PCB as well as PIC. The infrared and visible cameras used in this work have different field of view, therefore, after applying morphological methods, we performed image registration to synchronize both visible and thermal images. We demonstrate this method on the circuit board with active electrical/photonic elements and were able to observe thermal profile of these components.


2017 ◽  
Vol 2017 (1) ◽  
pp. 000652-000658
Author(s):  
Mimi X. Yang ◽  
Karen Dowling ◽  
Debbie Senesky ◽  
H.-S. Philip Wong

Abstract This works describes a promising method for rapid prototyping tape stencils for the application of solder paste. This process is appropriate for research settings requiring developmental flexibility and the ability to deal with small device dies. This work compares the volume of solder paste deposited versus aperture volume for several common tape materials and several common printed circuit board (PCB) stencil materials. The solder deposits are then reflowed to identify which aperture and solder paste parameters can generate successful solder bumps. Electrically conductive solder bonds for small bond pads (100 μm and larger) are demonstrated between silicon device dies and glass dies using this process.


2017 ◽  
Vol 31 (16-19) ◽  
pp. 1744008
Author(s):  
M. Meng ◽  
Z. B. Wang ◽  
X. Wang ◽  
Y. Chen

This paper analyzes two failure cases of creep-caused fracture of PbSn solder joint, including the joint between the wire and solder cup in the connector and the joint between the integrated circuit (IC) pins and the printed circuit board (PCB). The environment conditions, for the creep of PbSn solder joint is demonstrated, including the temperature and stress level. The stress origin and fracture morphology are summarized based on the failure analysis. Besides, the developing process of creep-caused fracture is explained. The paper comprehensively clarifies the creep mechanism of PbSn solder and consequently provides significant guidance for the reliable electronic assembly to avoid the creep-caused damage.


2021 ◽  
Vol 17 (3) ◽  
pp. 1-28
Author(s):  
Shubhra Deb Paul ◽  
Swarup Bhunia

A printed circuit board (PCB) provides necessary mechanical support to an electronic system and acts as a platform for connecting electronic components. Counterfeiting and in-field tampering of PCBs have become significant security concerns in the semiconductor industry as a result of increasing untrusted entities in the supply chain. These counterfeit components may result in performance degradation, profit reduction, and reputation risk for the manufacturers. While Integrated Circuit (IC) level authentication using physical unclonable functions (PUFs) has been widely investigated, countermeasures at the PCB level are scarce. These approaches either suffer from significant overhead issues, or opportunistic counterfeiters can breach them like clockwork. Besides, they cannot be extended to system-level (both chip and PCB together), and their applications are also limited to a specific purpose (i.e., either counterfeiting or tampering). In this article, we introduce SILVerIn , a novel systematic approach to verify the authenticity of all chips used in a PCB as well as the board for combating attacks such as counterfeiting, cloning, and in-field malicious modifications. We develop this approach by utilizing the existing boundary scan architecture (BSA) of modern ICs and PCBs. As a result, its implementation comes at a negligible (∼0.5%) hardware overhead. SILVerIn  is integrated into a PCB design during the manufacturing phase. We implement our technique on a custom hardware platform consisting of an FPGA and a microcontroller. We incorporate the industry-standard JTAG (Joint Test Action Group) interface to transmit test data into the BSA and perform hands-on measurement of supply current at both chip and PCB levels on 20 boards. We reconstruct these current values to digital signatures that exhibit high uniqueness, robustness, and randomness features. Our approach manifests strong reproducibility of signatures at different supply voltage levels, even with a low-resolution measurement setup. SILVerIn  also demonstrates a high resilience against machine learning-based modeling attacks, with an average prediction accuracy of ∼51%. Finally, we conduct intentional alteration experiments by replacing the on-board FPGA to replicate the scenario of PCB tampering, and the results indicate successful detection of in-field modifications in a PCB.


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