scholarly journals Growth of high-quality semiconducting tellurium films for high-performance p-channel field-effect transistors with wafer-scale uniformity

2022 ◽  
Vol 6 (1) ◽  
Author(s):  
Taikyu Kim ◽  
Cheol Hee Choi ◽  
Pilgyu Byeon ◽  
Miso Lee ◽  
Aeran Song ◽  
...  
Keyword(s):  
Field Effect ◽  
Physical Vapor Deposition ◽  
High Performance ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Three Dimensional ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Wafer Scale

AbstractAchieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm2 V−1 s−1 and an ION/OFF ratio of 5.8 × 105 with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.

scholarly journals Design and Analysis of CMOS and CNTFET based Ternary Operators for Scrambling

2019 ◽  
Vol 4 (5) ◽  
pp. 575-579
Author(s):  
Gudala Konica . ◽  
Sreenivasulu Mamilla .
Keyword(s):  
Energy Efficient ◽  
Field Effect ◽  
High Performance ◽  
Digital Circuits ◽  
Performance Metrics ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Future Generations ◽  
Power Delay Product

As silicon technology scales down, it is a dominant choice to have high-performance digital circuits. As researchers investigated for high-performance digital circuits for future generations, Carbon Nanotube Field Effect Transistors (CNTFETs) is considered as the most promising technology due to their excellent current driving capability and proved to be an alternative to conventional CMOS technology. A CNTFET based energy efficient ternary operators are proposed for scrambling applications. The transistor-level implementations of operators namely Scrambling Operator1 (SOP1), Scrambling Operator2 (SOP2) and SUM operators are simulated with CMOS and CNTFET in 32 nm technology at 0.9 V supply voltage using Synopsys HSPICE. The performance metrics like Power, Delay and Power-delay product (PDP) are measured and a comparative analysis for CNTFET and CMOS technologies is carried out. The results demonstrate that CNTFET designs have better-optimized results in power, energy consumption, and reduced transistor count.

scholarly journals Polarization-sensitive photodetectors based on three-dimensional molybdenum disulfide (MoS2) field-effect transistors

Nanophotonics ◽  
2020 ◽  
Vol 9 (16) ◽  
pp. 4719-4728
Author(s):  
Tao Deng ◽  
Shasha Li ◽  
Yuning Li ◽  
Yang Zhang ◽  
Jingye Sun ◽  
...  
Keyword(s):  
Molybdenum Disulfide ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Three Dimensional ◽  
Polarized Light ◽  
Optical Field ◽  
Two Dimensional ◽  
Polarization Ratio ◽  
Two Dimensional Materials

AbstractThe molybdenum disulfide (MoS2)-based photodetectors are facing two challenges: the insensitivity to polarized light and the low photoresponsivity. Herein, three-dimensional (3D) field-effect transistors (FETs) based on monolayer MoS2 were fabricated by applying a self–rolled-up technique. The unique microtubular structure makes 3D MoS2 FETs become polarization sensitive. Moreover, the microtubular structure not only offers a natural resonant microcavity to enhance the optical field inside but also increases the light-MoS2 interaction area, resulting in a higher photoresponsivity. Photoresponsivities as high as 23.8 and 2.9 A/W at 395 and 660 nm, respectively, and a comparable polarization ratio of 1.64 were obtained. The fabrication technique of the 3D MoS2 FET could be transferred to other two-dimensional materials, which is very promising for high-performance polarization-sensitive optical and optoelectronic applications.

scholarly journals Three-Dimensional Nanoscale Mapping of State-of-the-Art Field-Effect Transistors (FinFETs)

2017 ◽  
Vol 23 (5) ◽  
pp. 916-925
Author(s):  
Pritesh Parikh ◽  
Corey Senowitz ◽  
Don Lyons ◽  
Isabelle Martin ◽  
Ty J. Prosa ◽  
...  
Keyword(s):  
Field Effect ◽  
Focused Ion Beam ◽  
Field Effect Transistors ◽  
Ion Beam ◽  
Semiconductor Industry ◽  
Three Dimensional ◽  
Atom Probe ◽  
Physical Structure ◽  
Oxide Semiconductor ◽  
Device Performance

AbstractThe semiconductor industry has seen tremendous progress over the last few decades with continuous reduction in transistor size to improve device performance. Miniaturization of devices has led to changes in the dopants and dielectric layers incorporated. As the gradual shift from two-dimensional metal-oxide semiconductor field-effect transistor to three-dimensional (3D) field-effect transistors (finFETs) occurred, it has become imperative to understand compositional variability with nanoscale spatial resolution. Compositional changes can affect device performance primarily through fluctuations in threshold voltage and channel current density. Traditional techniques such as scanning electron microscope and focused ion beam no longer provide the required resolution to probe the physical structure and chemical composition of individual fins. Hence advanced multimodal characterization approaches are required to better understand electronic devices. Herein, we report the study of 14 nm commercial finFETs using atom probe tomography (APT) and scanning transmission electron microscopy–energy-dispersive X-ray spectroscopy (STEM-EDS). Complimentary compositional maps were obtained using both techniques with analysis of the gate dielectrics and silicon fin. APT additionally provided 3D information and allowed analysis of the distribution of low atomic number dopant elements (e.g., boron), which are elusive when using STEM-EDS.

The Effect of Strain on the Formation of Dislocations at the SiGe/Si Interface

MRS Bulletin ◽  
1996 ◽  
Vol 21 (4) ◽  
pp. 38-44 ◽  
Author(s):  
F.K. LeGoues
Keyword(s):  
Metal Oxide ◽  
High Speed ◽  
High Performance ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Design Rule ◽  
Strained Si

Recently much interest has been devoted to Si-based heteroepitaxy, and in particular, to the SiGe/Si system. This is mostly for economical reasons: Si-based technology is much more advanced, is widely available, and is cheaper than GaAs-based technology. SiGe opens the door to the exciting (and lucrative) area of Si-based high-performance devices, although optical applications are still limited to GaAs-based technology. Strained SiGe layers form the base of heterojunction bipolar transistors (HBTs), which are currently used in commercial high-speed analogue applications. They promise to be low-cost compared to their GaAs counterparts and give comparable performance in the 2-20-GHz regime. More recently we have started to investigate the use of relaxed SiGe layers, which opens the door to a wider range of application and to the use of SiGe in complementary metal oxide semiconductor (CMOS) devices, which comprise strained Si and SiGe layers. Some recent successes include record-breaking low-temperature electron mobility in modulation-doped layers where the mobility was found to be up to 50 times better than standard Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Even more recently, SiGe-basedp-type MOSFETS were built with oscillation frequency of up to 50 GHz, which is a new record, in anyp-type material for the same design rule.

High Performance Organic Field-Effect Transistors and Integrated Inverters

2001 ◽  
Vol 665 ◽  
Author(s):  
A. Ullmann ◽  
J. Ficker ◽  
W. Fix ◽  
H. Rost ◽  
W. Clemens ◽  
...  
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Drain Current ◽  
Organic Field Effect Transistors ◽  
Metal Contacts ◽  
Gate Electrodes ◽  
Polymer Semiconductors ◽  
Set Up

ABSTRACTIntegrated plastic circuits (IPCs) will become an integral component of future low cost electronics. For low cost processes IPCs have to be made of all-polymer Transistors. We present our recent results on fabrication of Organic Field-Effect Transistors (OFETs) and integrated inverters. Top-gate transistors were fabricated using polymer semiconductors and insulators. The source-drain structures were defined by standard lithography of Au on a flexible plastic film, and on top of these electrodes, poly(3-alkylthiophene) (P3AT) as semiconductor, and poly(4-hydroxystyrene) (PHS) as insulator were homogeneously deposited by spin-coating. The gate electrodes consist of metal contacts. With this simple set-up, the transistors exhibit excellent electric performance with a high source-drain current at source - drain and gate voltages below 30V. The characteristics show very good saturation behaviour for low biases and are comparable to results published for precursor pentacene. With this setup we obtain a mobility of 0.2cm2/Vs for P3AT. Furthermore, we discuss organic integrated inverters exhibiting logic capability. All devices show shelf-lives of several months without encapsulation.

scholarly journals A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator

Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 223 ◽  
Author(s):  
Yannan Zhang ◽  
Ke Han ◽  
and Jiawei Li
Keyword(s):  
Metal Oxide ◽  
Low Power ◽  
Energy Efficient ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Future Generation ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Ultra Low Power

Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices.

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