An interface trap charge model for simulation of graphene-based synaptic field effect transistors

Interface traps between a gate insulator and beta-gallium oxide (β-Ga2O3) channel are extensively studied because of the interface trap charge-induced instability and hysteresis. In this work, their effects on mobility degradation at low temperature and hysteresis at high temperature are investigated by characterizing electrical properties of the device in a temperature range of 20–300 K. As acceptor-like traps at the interface are frozen below 230 K, the hysteresis becomes negligible but simultaneously the channel mobility significantly degrades because the inactive neutral traps allow additional collisions of electrons at the interface. This is confirmed by the fact that a gate bias adversely affects the channel mobility. An activation energy of such traps is estimated as 170 meV. The activated trap charges’ trapping and de-trapping processes in response to the gate pulse bias reveal that the time constants for the slow and fast processes decrease due to additionally activated traps as the temperature increases.

Download Full-text

Interface trap density and mobility extraction in InGaAs buried quantum well metal-oxide-semiconductor field-effect-transistors by gated Hall method

Applied Physics Letters ◽

10.1063/1.4870257 ◽

2014 ◽

Vol 104 (13) ◽

pp. 131605 ◽

Cited By ~ 3

Author(s):

Thenappan Chidambaram ◽

Dmitry Veksler ◽

Shailesh Madisetti ◽

Andrew Greene ◽

Michael Yakimov ◽

...

Keyword(s):

Quantum Well ◽

Metal Oxide ◽

Field Effect ◽

Field Effect Transistors ◽

Metal Oxide Semiconductor ◽

Trap Density ◽

Oxide Semiconductor ◽

Interface Trap Density ◽

Interface Trap ◽

Hall Method

Download Full-text

Interface Trap Charge Effects of Monolithic 3D Junctionless Field-Effect Transistors (JLFET) Inverter

Journal of Nanoscience and Nanotechnology ◽

10.1166/jnn.2021.19388 ◽

2021 ◽

Vol 21 (8) ◽

pp. 4252-4257

Author(s):

Tae Jun Ahn ◽

Yun Seop Yu

Keyword(s):

Computer Aided Design ◽

Field Effect Transistors ◽

Three Dimensional ◽

Interface Trap ◽

Charge Effects ◽

Trap Charge ◽

Interlayer Dielectric ◽

Threshold Voltages ◽

Propagation Delays ◽

Aided Design

We investigated the effect of the interface trap charge in a monolithic three-dimensional inverter structure composing of JLFETs (M3DINV-JLFET), using the interface trap charge distribution extracted in the previous study. The effect of interface trap charge was compared with a conventional M3DINV composing of MOSFETs (M3DINV-MOSFETs) by technology computer-aided design simulation. When the interface trap charges in both M3DINV-JLFET and M3DINV-MOSFET are added, the threshold voltages, on-current levels, and subthreshold swings of both JLFETs and MOSFETs increase, decrease, and increase, respectively, and switching voltages and propagation delays of M3DINV are shifted and increased, respectively. However, since JLFET and MOSFET have different current paths of bulk and interface in channel, respectively, MOSFET is more affected by the interface trap, and M3DINV-JLFET has almost less effect of interface trap at different thickness of interlayer dielectric, compared to M3DINV-MOSFET.

Download Full-text