scholarly journals The High-Speed Low-Power Dynamic Comparator

2021 ◽  
Vol 2113 (1) ◽  
pp. 012064
Author(s):  
Menghua Cao ◽  
Weixun Tang
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Positive Feedback ◽  
High Speed ◽  
Low Noise ◽  
Dynamic Comparator ◽  
Low Delay ◽  
Offset Voltage ◽  
A Charge ◽  
Definition Phase

Abstract This paper comments on four works for the optimization of comparator design. Today, with the development of integrated circuits, the requirements for comparators about low power, low delay, few offset voltage, and low noise are highly desirable. Specifically, these works made progress in the conventional comparator, which comprises a preamplifier and a latch. They also solved some problems, such as decreasing power and delay. Some works employ a positive feedback cross-coupled pares to provide a larger gain in the preamplifier, use PMOS switch transistors to accelerate the definition phase, or a double-tail architecture to increase the latch regeneration speed. Other work designs a charge pump to improve speed.

scholarly journals An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

Electronics ◽  
2018 ◽  
Vol 8 (1) ◽  
pp. 13 ◽  
Author(s):  
Athanasios Ramkaj ◽  
Maarten Strackx ◽  
Michiel Steyaert ◽  
Filip Tavernier
Keyword(s):  
High Resolution ◽  
High Speed ◽  
State Of The Art ◽  
Low Noise ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Ideal Candidate ◽  
Offset Voltage ◽  
Multi Stage ◽  
28 Nm

This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred offset voltage by a factor of ten compared to the uncalibrated value without any speed or noise penalty and with less than 5% power overhead. Moreover, the implemented multi-stage topology significantly advances the state-of-the-art comparator performance, achieving the highest reported operating frequency, as well as the lowest delay slope and sensitivity to supply and common mode variations compared to existing works, with similar energy/comparison. This makes the proposed self-calibrating comparator an ideal candidate for high resolution (>10 b) multi-GHz Analog-to-Digital Converters (ADCs). The 28 nm bulk CMOS prototype measures an input-referred noise and calibrated offset of 0.82 mV and 0.99 mV, respectively clocked at 11 GHz, consuming only 0.89 mW from a 1 V supply, for an area of 0.00054 mm2, including calibration.

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

A Linearity Improved 10-bit 120-MS/s 1.5 mW SAR ADC with High-Speed and Low-Noise Dynamic Comparator Technique

2019 ◽  
Vol 29 (06) ◽  
pp. 2050084
Author(s):  
Daiguo Xu ◽  
Hequan Jiang ◽  
Dongbin Fu ◽  
Xiaoquan Yu ◽  
Shiliu Xu ◽  
...  
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Low Noise ◽  
Sar Adc ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Input Noise ◽  
Clock Feedthrough ◽  
Threshold Voltages ◽  
Coupled Technique

This paper presents a linearity improved 10-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with high-speed and low-noise dynamic comparator. A gate cross-coupled technique is introduced in boost sampling switch, the clock feedthrough effect is compensated without extra auxiliary switch and the linearity of sampling switch is enhanced. Further, substrate voltage boost technique is proposed, the absolute values of threshold voltage and equivalent impedances of MOSFETs are both depressed. Consequently, the delay of comparator is also reduced. Moreover, the reduction of threshold voltages for input MOSFETs could bring higher transconductance and lower equivalent input noise. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 1.5[Formula: see text]mW from 1[Formula: see text]V power supply with a SNDR [Formula: see text][Formula: see text]dB and SFDR [Formula: see text][Formula: see text]dB. The proposed ADC core occupies an active area of 0.021[Formula: see text]mm2, and the corresponding FoM is 24.4 fJ/conversion-step with Nyquist frequency.

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