scholarly journals Performance analysis of cost effective multi-hop Time Sensitive Network for IEEE 802.1Qbv and IEEE 802.1Qbu standards

2022 ◽  
Vol 2161 (1) ◽  
pp. 012002
Author(s):  
Asha G Hagargund ◽  
Muralidhar kulkarni ◽  
Hariram S Satheesh
Keyword(s):  
Performance Analysis ◽  
Cost Effective ◽  
Emerging Technology ◽  
The Novel ◽  
Vehicle Communication ◽  
Vehicle To Vehicle ◽  
Simulation Based ◽  
Ieee Standards ◽  
Simulation Results ◽  
Time Critical

Abstract Time-Sensitive Networking (TSN) is an emerging technology, which enables advancements in applications like industrial automation, automatic vehicle-to-vehicle communication, etc. which hosts various time-critical applications, ensuring bounded latency. The novel idea of this paper is to present OMNET++ simulation-based complex multi-hop TSN network using the native VLAN concept to bring out a cost-effective model for inter-TSN and Intra-TSN domains. This paper investigates the performance of hybrid IEEE standards, ie.IEEE 802.1Qbu and IEEE 802.1Qbv standards. The simulation results show that the combination of these standards, when effectively scheduled in switches will reduce the latency by 3.3 µseconds in time-critical applications. Further, it is observed that in Best effort traffic, frame loss is also very less in the range of 2-5 frames out of 1385 frames. These results certainly will be of great value in more complex TSN deployments.

A Novel 3-DOF Parallel Robot and its Kinematic Analysis

2014 ◽  
Vol 607 ◽  
pp. 759-763
Author(s):  
Xiao Bo Liu ◽  
Xiao Dong Yuan ◽  
Xiao Feng Wei ◽  
Wei Ni
Keyword(s):  
Motion Control ◽  
Kinematic Analysis ◽  
Degrees Of Freedom ◽  
Parallel Robot ◽  
Degree Of Freedom ◽  
The Novel ◽  
Forward Displacement ◽  
Simulation Based ◽  
Simulation Results

This paper deals with the design and analysis of a novel and simple two-translation and one-rotation (3 degrees of freedom, 3-dof) mechanism for alignment. Firstly, degree of freedom of the parallel robot is solved based on the theory of screw. Secondly considering the demand of motion control, we have conducted the analysis on the 3-dof parallel robot, which includes inverse displacement, forward displacement, and simulation based on SolidWorks Motion. The simulation results indicate that the novel 3-dof robot is suitable for performing the required operations.

scholarly journals Authentication-Based Vehicle-to-Vehicle Secure Communication for VANETs

2019 ◽  
Vol 2019 ◽  
pp. 1-9
Author(s):  
Huibin Xu ◽  
Mengjia Zeng ◽  
Wenjun Hu ◽  
Juan Wang
Keyword(s):  
Performance Analysis ◽  
Secure Communication ◽  
Operation Time ◽  
Communication Cost ◽  
Storage Space ◽  
Security Attacks ◽  
Variable Parameters ◽  
Vehicle Communication ◽  
Vehicle To Vehicle ◽  
Lightweight Authentication

Communication in VANETs is vulnerable to various types of security attacks since it is constructed based on an open wireless connection. Therefore, a lightweight authentication (LIAU) scheme for vehicle-to-vehicle communication is proposed in this paper. The LIAU scheme requires hash operations and uses cryptographic concepts to transfer messages between vehicles, in order to maintain the required security. Moreover, we made the LIAU scheme lightweight by introducing a small number of variable parameters in order to reduce the storage space. Performance analysis shows that the LIAU scheme is able to resist various types of security attacks and it performs well in terms of communication cost and operation time.

FPGA Based Vehicle to Vehicle Communication in Spartan 3E

2020 ◽  
Vol 8 ◽  
pp. 14-21
Author(s):  
Surya Man Koju ◽  
Nikil Thapa
Keyword(s):  
Signal Processing ◽  
Autonomous Vehicle ◽  
Processing Unit ◽  
Warning Signals ◽  
Vehicle Communication ◽  
Digital Vlsi ◽  
Vehicle To Vehicle ◽  
Vehicle Operation ◽  
Vehicle Technology ◽  
The Voice

This paper presents economic and reconfigurable RF based wireless communication at 2.4 GHz between two vehicles. It implements digital VLSI using two Spartan 3E FPGAs, where one vehicle receives the information of another vehicle and shares its own information to another vehicle. The information includes vehicle’s speed, location, heading and its operation, such as braking status and turning status. It implements autonomous vehicle technology. In this work, FPGA is used as central signal processing unit which is interfaced with two microcontrollers (ATmega328P). Microcontroller-1 is interfaced with compass module, GPS module, DF Player mini and nRF24L01 module. This microcontroller determines the relative position and the relative heading as seen from one vehicle to another. Microcontroller-2 is used to measure the speed of vehicle digitally. The resulting data from these microcontrollers are transmitted separately and serially through UART interface to FPGA. At FPGA, different signal processing such as speed comparison, turn comparison, distance range measurement and vehicle operation processing, are carried out to generate the voice announcement command, warning signals, event signals, and such outputs are utilized to warn drivers about potential accidents and prevent crashes before event happens.

scholarly journals Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 759
Author(s):  
Edel Díaz ◽  
Raúl Mateos ◽  
Emilio J. Bueno ◽  
Rubén Nieto
Keyword(s):  
Performance Analysis ◽  
Industrial Application ◽  
The Novel ◽  
San Jose ◽  
Synchronization Mechanism ◽  
Grid Monitoring ◽  
Parallel Mode ◽  
Software And Hardware ◽  
Software Emulator ◽  
Dual Core

Presently, the trend is to increase the number of cores per chip. This growth is appreciated in Multi-Processor System-On-Chips (MPSoC), composed of more cores in heterogeneous and homogeneous architectures in recent years. Thus, the difficulty of verification of this type of system has been great. The hardware/software co-simulation Virtual Platforms (VP) are presented as a perfect solution to address this complexity, allowing verification by simulation/emulation of software and hardware in the same environment. Some works parallelized the software emulator to reduce the verification times. An example of this parallelization is the QEMU (Quick EMUlator) tool. However, there is no solution to synchronize QEMU with the hardware simulator in this new parallel mode. This work analyzes the current software emulators and presents a new method to allow an external synchronization of QEMU in its parallelized mode. Timing details of the cores are taken into account. In addition, performance analysis of the software emulator with the new synchronization mechanism is presented, using: (1) a boot Linux for MPSoC Zynq-7000 (dual-core ARM Cortex-A9) (Xilinx, San Jose, CA, USA); (2) an FPGA-Linux co-simulation of a power grid monitoring system that is subsequently implemented in an industrial application. The results show that the novel synchronization mechanism does not add any appreciable computational load and enables parallelized-QEMU in hardware/software co-simulation virtual platforms.

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