scholarly journals Design and Implementation of Power-Efficient FSM based UART

2022 ◽  
Vol 2161 (1) ◽  
pp. 012052
Author(s):  
Akshatha Kamath ◽  
Tanya Mendez ◽  
S Ramya ◽  
Subramanya G Nayak
Keyword(s):  
High Speed ◽  
Data Communication ◽  
Total Power ◽  
Clock Frequency ◽  
General Process ◽  
Baud Rate ◽  
Power Efficient ◽  
Vlsi Chip ◽  
Finite State ◽  
Power Delay Product

Abstract The remarkable innovations in technology are driven mainly by the high-speed data communication requirements of the modern generation. The Universal Asynchronous Receiver Transmitter (UART) is one of the most sought-after communication protocols. This work mainly focuses on implementing and analysing the UART for data communication. The Finite State Machine (FSM) implements the baud rate generator, transmitter, and receiver modules. Cadence NCSIM was utilized for simulation, and Cadence RTL Compiler was used during synthesis using the 45 nm and 90 nm General Process Design Kit (GPDK) library files. The baud rate of 9600 bps and 50 MHz clock frequency was used to design UART. The increased speed and complexity of the VLSI chip designs has resulted in a significant increase in power consumption. The comparative analysis of power and delay for different clock periods shows an improvement in the total power and the Power Delay Product (PDP) with increasing clock periods. Better results were observed using 45 nm in comparison to the 90 nm library.

Sleepy CMOS-Sleepy Stack (SC-SS): A Novel High Speed, Area and Power Efficient Technique for VLSI Circuit Design

2019 ◽  
Vol 28 (12) ◽  
pp. 1950197 ◽  
Author(s):  
Anjali Sharma ◽  
Harsh Sohal ◽  
Harsimran Jit Kaur
Keyword(s):  
Circuit Design ◽  
Power Efficiency ◽  
High Speed ◽  
Total Power ◽  
Ultra Low Power ◽  
Xor Gate ◽  
Power Efficient ◽  
Area Product ◽  
Power Delay Product ◽  
Very High

This paper presents a novel ultra-low-power Sleepy CMOS-Sleepy Stack (SC-SS) technique for nano scale VLSI technologies. Eight prior techniques are taken for comparison with proposed technique on 65[Formula: see text]nm technology. All the techniques are applied on four benchmark circuits: XOR gate, 1-bit adder, 1-bit comparator and 4-bit up-down counter for measurement of area consumption and total power dissipation. The proposed SC-SS technique achieved very high power efficiency as compared to Complementary CMOS technique (CCT), Dual sleep Technique (DST), Forced stack technique (FST), Sleepy keeper technique (SKT), Sleepy pass gate technique (SPGT), Sleep transistor technique (STT) and VLSI CMOS Circuit Leakage Reduction technique (VCLEARIT). Although Sleepy stack technique (SST) is power efficient as compared to SC-SS technique, this is on the expense of area and delay penalty. Proposed technique has shown the area improvement of 33% for XOR, 10.78 % for 1-bit adder, 14.9% for 1-bit comparator and 9.7% for 4-bit up-down counter over SST technique on 65[Formula: see text]nm technology. At the same time, power-area product of SC-SS is 29.56% and 54.96% less as compared to SST for XOR and 4-bit up-down counter. To obtain the efficiency of proposed technique over SST in terms of delay and power-delay product, basic inverter design is taken into consideration. Delay of SC-SS inverter is 34.8% and power-delay product is 6.9% less as compared to SST inverter on 65[Formula: see text]nm technology.

Area Efficient Carry Select Adder Using Negative Edge Triggered D-Flipflop

2014 ◽  
Vol 573 ◽  
pp. 187-193 ◽  
Author(s):  
Anitha Ponnusamy ◽  
Palaniappan Ramanathan
Keyword(s):  
Integrated Circuit ◽  
Power Dissipation ◽  
High Speed ◽  
Total Power ◽  
Single Chip ◽  
Flip Flop ◽  
Design And Optimization ◽  
Negative Edge ◽  
Carry Select Adder ◽  
Power Delay Product

The recent increase in popularity of portable systems and rapid growth of packaging density in VLSI circuit’s has enable designers to design complex functional units on a single chip. Power, area and speed plays a major role in the design and optimization of an integrated circuit. Carry select adder is high speed final stage adder widely used in many data processing units. In this work, conventional D-flip flop is replaced by a new design using negative edge triggered D-flip flop. The proposed CSA is implemented in a faster partitioned Dadda multiplier and simulated by using MICROWIND tool. The results reveal that for 16 bit CSA improvement of power delay product (PDP) of the proposed design using negative edge triggered D flip flop is 78% & 18% when compared to CSA with BEC and CSA with conventional D flip flop. When CSA implemented in a partitioned Dadda multiplier it results in performance improvement of 74 % with little increase in total power dissipation.

scholarly journals Design and Implementation of Carbon Nano-tube based Full Adder at 32nm Technology for High Speed and Power Efficient Arithmetic Applications

2022 ◽  
Vol 2161 (1) ◽  
pp. 012050
Author(s):  
Imran Ahmed Khan
Keyword(s):  
High Speed ◽  
Full Adder ◽  
Logic Circuits ◽  
Power Efficient ◽  
Cmos Transistors ◽  
Bases Of Power ◽  
Ripple Carry Adder ◽  
Supply Voltages ◽  
Power Delay Product ◽  
Carbon Nano Tube

Abstract Due to physical, material, technological, power-thermal and economical difficulties, scaling of CMOS transistors will stop very soon. Due to efficiency of power and speed compared to CMOS transistors, Carbon Nano-tube transistors are best suitable element to design logic circuits. So, CNTFETS have been utilized in designing of proposed full adder (FA) and 4-bit ripple carry adder (RCA) in this paper. Proposed FA and RCA have been compared to rival designs on bases of power, speed and power-delay-product (PDP). FA and RCA circuits have been analysed with the variation of temperature from 0°C to 100°C while the variation of supply voltages is from 0.7V to 1.3V. For all temperatures and all supply voltages, proposed FA and proposed RCA have the least power consumption, shortest delay and lowest PDP. SPICE has been utilized for simulating FAs and RCAs in 32 nm process node. Even though the fabrication is complicated than CMOS counterparts but simulation results confirm usefulness of proposed FA and RCA for high speed and power efficient arithmetic applications.

Design of low power and high speed implicit pulse flip-flop and its application

2018 ◽  
Vol 7 (3) ◽  
pp. 1893 ◽  
Author(s):  
Kuruvilla John ◽  
Vinod Kumar R S ◽  
Kumar S S
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Product Performance ◽  
Power Performance ◽  
Flip Flop ◽  
Power Efficient ◽  
Pass Transistor ◽  
Simulation Results ◽  
Power Delay Product ◽  
Pmos Transistor

In this paper, a new power efficient and high speed pulsed-triggered flip-flop in implicit style with conditional pulse enhancement and signal feed-through (CPESFTFF) is proposed. This novel architecture is presented for the pulse-triggered D-FF in the CMOS 90-nm technology. Two important features are embedded in this flip-flop architecture. Firstly, a conditional enhancement in width and height of the triggering pulses by using an additional pMOS transistor in the structure is done. Secondly, a modified signal feed-through mechanism which directly samples the input to output by using an nMOS pass transistor is introduced. The proposed design achieves better speed and power performance by successfully solving the longest discharging path problem. The simulation results show that the proposed architecture has improvement in terms of power consumption, D-to-Q delay, and Power Delay Product Performance (PDP) in comparison with other conventional P-FF architectures. A 3-bit up counter is also implemented using proposed P-FF.  

scholarly journals Power Efficient Clock Distribuition for Switched Capacitor DC-DC Converters

2018 ◽  
Vol 10 (1) ◽  
pp. 27
Author(s):  
A. S. R. Murthy ◽  
Sridhar T.
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
Power Distribution ◽  
High Speed ◽  
Low Voltage ◽  
Data Communication ◽  
Distribution Networks ◽  
Propagation Delay ◽  
Switched Capacitor ◽  
Power Efficient

<p>In various VLSI based digital systems, on-chip interconnects have become the system bottleneck in state-of-the-art chips, limiting the performance of high-speed clock distributions and data communication devices in terms of propagation delay and power consumption. Increasing power requirements and power distribution to multi-core architectures is also posing a challenge to power distribution networks in the integrated circuits. Clock distribution networks for the switched capacitor converters becomes a non-trivial task and the increased interconnect lengths cause clock degradation and power dissipation. Therefore, this paper introduce low swing signaling schemes to decrease delay and power consumption. A comparative study presented of low voltage signaling schemes in terms of delay, power consumption and power delay product. Here, we have presented a power efficient signaling topology for driving the clocks to higher interconnect lengths.</p>

Gate Diffusion Input Based 10-T CNTFET Power Efficient Full Adder

2021 ◽  
Vol 14 ◽  
Author(s):  
Priyanka Tyagi ◽  
Sanjay Kumar Singh ◽  
Piyush Dua
Keyword(s):  
High Speed ◽  
Full Adder ◽  
Additional Advantage ◽  
Power Efficient ◽  
Digital World ◽  
Diffusion Technique ◽  
Low Power Dissipation ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Full Swing

Background: Full adder is the key element of the digital electronics. The CNTFET is the most promising device in modern electronics. To enhance the performance of the full adder CNTFET is used in place of the CMOS. Objective: To implement the high speed full adder circuit for advance applications of the digital world. Methods: Full adder circuit with new Gate diffusion technique has been implemented in this work. There is the comparative study of the 10-T CNTFET full adder with GDI technique and the 10-T Finfet based full adder using GDI technique. Ultralow power feature is the additional advantage of the GDI technique. This technology provides the full swing voltage to the circuit moreover it also reduces number of transistors required. This technique has been used with CNTFET to upgrade full adder in terms of the dissipated power and product of power consumed and delay introduced in the circuit. Results: The proposed design shows that the low power dissipation comes out to be approximately 4.3nW at 0.5volts. The power delay product is 4.7x10-20 J at the same voltage level. The Finfet design also shows the better performance with GDI. But GDI enhance CNTFET based design power consumption about 32% from the FinFET. Conclusions: CNTFET observed the better response due to good current conductivity as compare to the FinFET. This work has been implemented and simulated on the 32nm node technology.

Improved Domino Logic Circuits and its Application in Wide Fan-In OR Gates

2020 ◽  
Vol 12 (1) ◽  
pp. 58-67
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Brahamdeo Prasad Singh ◽  
Ajay Kumar
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Performance ◽  
Voltage Drop ◽  
Main Concern ◽  
Clock Frequency ◽  
Domino Logic ◽  
Evaluation Phase ◽  
Power Delay Product ◽  
Domino Circuits

Background: Main concern in efficient VLSI circuit designing is low-power consumption, high-speed and noise tolerance capability. Objective: In this paper, two efficient and high-performance topologies are proposed for cascaded domino logic using carbon nanotube MOSFETs (CN-MOSFETs). The first topology is designed to remove the intermediate charge sharing problem without any keeper circuit, whereas the second one holds the true logic level of the evaluation phase without any voltage drop for next precharge phase. The proposed topologies are suitable for cascading of the high-performance domino circuits. Methods: The proposed domino circuits are tested and verified using Synopsys HSPICE simulator with 32nm CN-MOSFET technology provided by Stanford University. Conclusion: The power delay product of proposed DL-I and DL-II improves by 32.59 % and 40.98 % for 8-input OR gate as compared to standard logic respectively at the clock frequency of 500 MHz. The simulation results validate that the proposed circuits improve the performance of pseudo domino logic with respect to leakage power consumption, delay and unity noise gain.

scholarly journals Electrically Driven Micro- and Nano-Scale Semiconductor Light Sources

2019 ◽  
Vol 9 (4) ◽  
pp. 802 ◽  
Author(s):  
You-Shin No
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Data Communication ◽  
Essential Element ◽  
Light Sources ◽  
Photonic Integrated Circuit ◽  
Power Efficient ◽  
Light Emitting Devices ◽  
Nano Scale ◽  
On Chip

Emerging optical technology capable of addressing the limits in modern electronics must incorporate unique solutions to bring about a revolution in high-speed, on-chip data communication and information processing. Among the possible optical devices that can be developed, the electrically driven, ultrasmall semiconductor light source is the most essential element for a compact, power-efficient photonic integrated circuit. In this review, we cover the recent development of the electrically driven light-emitting devices based on various micro- and nano-scale semiconductor optical cavities. We also discuss the recent advances in the integration of these light sources with passive photonic circuits.

scholarly journals VLSI Implementation of Green Computing Control Unit on Zynq FPGA for Green Communication

2021 ◽  
Vol 2021 ◽  
pp. 1-10
Author(s):  
Anurag Shrivastava ◽  
Ali Rizwan ◽  
Neelam Sanjeev Kumar ◽  
R. Saravanakumar ◽  
Inderjit Singh Dhanoa ◽  
...  
Keyword(s):  
Power Consumption ◽  
Control Unit ◽  
Total Power ◽  
Processing Unit ◽  
Clock Frequency ◽  
Green Communication ◽  
Green Networking ◽  
Power Efficient ◽  
Total Power Consumption ◽  
5 Ghz

The issue of the energy shortage is affecting the entire planet. This is occurring because of massive population and industry growth around the world. As a result, the entire world is attempting to implement green networking systems and manufacture the power/energy efficient products. This research work discusses the green networking system technologies. This work introduces a power-efficient control unit (CU) design and implemented on the Zynq SoC (System on Chip) ultrascale field programmable gate array (FPGA). The VIVADO HLx Design Suite is used to simulate and analyze the CU model which is considered as one of the key components of central processing unit (CPU), used for data communication purposes. The CU is made suitable for the green communication by making it power-efficient. Therefore, the power consumption of the CU is analyzed for the various set frequency value ranging between 100 MHz and 5 GHz, and it is discovered that as the clock frequency rises up, the total power consumption also tends to get increased. The total power of the proposed model is reduced by 77.42%, 21.29%, and 17.93% from three models, respectively, being compared in the present paper. Final results shows that the CU is better suited to run at low frequencies to optimize power consumption.

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