Low Power Single-Bit Cache Memory Architecture

IOP Conference Series Materials Science and Engineering ◽

10.1088/1757-899x/1116/1/012136 ◽

2021 ◽

Vol 1116 (1) ◽

pp. 012136

Author(s):

Reeya Agrawal ◽

Neetu Faujdar ◽

Aditi Saxena

Keyword(s):

Low Power ◽

Cache Memory ◽

Memory Architecture

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A Class Project For Low Power Cache Memory Architecture

10.18260/1-2--6 ◽

2020 ◽

Author(s):

Yul Chu

Keyword(s):

Low Power ◽

Cache Memory ◽

Memory Architecture ◽

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Low Power Single Bit Cache Memory Architecture

Materials Today Proceedings ◽

10.1016/j.matpr.2021.02.725 ◽

2021 ◽

Author(s):

Reeya Agrawal ◽

Manish Kumar

Keyword(s):

Low Power ◽

Cache Memory ◽

Memory Architecture

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Low-Power High-Performance and Dynamically Configured Multi-Port Cache Memory Architecture

2007 International Conference on Electrical Engineering ◽

10.1109/icee.2007.4287320 ◽

2007 ◽

Author(s):

H. Bajwa ◽

X. Chen

Keyword(s):

Low Power ◽

High Performance ◽

Cache Memory ◽

Memory Architecture

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Analysis of Cache Memory Architecture Design Using Low-Power Reduction Techniques for Microprocessors

10.1007/978-981-16-4222-7_56 ◽

2021 ◽

pp. 495-503

Author(s):

Reeya Agrawal

Keyword(s):

Low Power ◽

Power Reduction ◽

Cache Memory ◽

Architecture Design ◽

Memory Architecture ◽

Reduction Techniques

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Cryptographic Side-Channels from Low-Power Cache Memory

Cryptography and Coding - Lecture Notes in Computer Science ◽

10.1007/978-3-540-77272-9_11 ◽

2007 ◽

pp. 170-184 ◽

Author(s):

Philipp Grabher ◽

Johann Großschädl ◽

Daniel Page

Keyword(s):

Low Power ◽

Cache Memory ◽

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Cache Memory Architecture for Core Processor

10.1007/978-981-16-5207-3_66 ◽

2021 ◽

pp. 809-820

Author(s):

Reeya Agrawal

Keyword(s):

Cache Memory ◽

Memory Architecture

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Split Memory Based Memory Architecture with Single-ended High Speed Sensing Circuit to Improve Cache Memory Performance

2020 6th International Conference on Signal Processing and Communication (ICSC) ◽

10.1109/icsc48311.2020.9182771 ◽

2020 ◽

Author(s):

Kirmender Singh ◽

Sajal Khanna

Keyword(s):

Memory Performance ◽

Cache Memory ◽

Memory Architecture

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Embedded Memory Architecture for Low-Power Application Processor

Integrated Circuits and Systems - Embedded Memories for Nano-Scale VLSIs ◽

10.1007/978-0-387-88497-4_2 ◽

2009 ◽

pp. 7-38 ◽

Author(s):

Hoi Jun Yoo ◽

Donghyun Kim

Keyword(s):

Low Power ◽

Memory Architecture ◽

Embedded Memory ◽

Application Processor ◽

Power Application

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Design and analysis of multiple port memory architecture for low power applications

2018 Conference on Signal Processing And Communication Engineering Systems (SPACES) ◽

10.1109/spaces.2018.8316348 ◽

2018 ◽

Author(s):

T. Subhashini ◽

M. Kamaraju ◽

K. Babulu

Keyword(s):

Low Power ◽

Memory Architecture

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Critical race-free low-power NAND match line content addressable memory tagged cache memory

IET Computers & Digital Techniques ◽

10.1049/iet-cdt:20070040 ◽

2008 ◽

Vol 2 (1) ◽

pp. 40 ◽

Author(s):

V. Chaudhary ◽

T.-H. Chen ◽

F. Sheerin ◽

L.T. Clark

Keyword(s):

Low Power ◽

Cache Memory ◽

Critical Race ◽

Content Addressable Memory

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