Design of ternary subtractor using multiplexers

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Tulasi Naga Jyothi Kolanti ◽  
Vasundhara Patel K.S.
Keyword(s):  
Field Effect Transistors ◽  
Process Variations ◽  
Propagation Delay ◽  
Channel Length ◽  
Binary Decision ◽  
Content Type ◽  
The Stability ◽  
Power Delay Product ◽  
Ternary Decision Diagram ◽  
Logic Functions

Purpose The purpose of this paper is to design multiplexers (MUXs) based on ternary half subtractor and full subtractor using carbon nanotube field-effect transistors. Design/methodology/approach Conventionally, the binary logic functions are developed by using the binary decision diagram (BDD) systems. Each node in BDD is replaced by 2:1 MUX to implement the digital circuits. Similarly, in the ternary decision diagram, each node has to be replaced by 3:1 MUX. In this paper, ternary transformed BDD is used to design the ternary subtractors using 2:1 MUXs. Findings The performance of the proposed ternary half subtractor and full subtractor using the 2:1 MUX are compared with the 3:1 MUX-based ternary circuits. It has been observed that the delay, power and power delay product values are reduced, respectively, by 67.6%, 84.3%, 94.9% for half subtractor and 67.7%, 70.1%, 90.3% for full subtractor. From the Monte Carlo simulations, it is observed that the propagation delay and power dissipation of the proposed subtractors are increased by increasing the channel length due to process variations. The stability test is also performed and observed that the stability increases as the channel length and diameter are increased. Originality/value The proposed half subtractor and full subtractor show better performance over the existing subtractors.

scholarly journals Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation

Micromachines ◽  
2020 ◽  
Vol 11 (9) ◽  
pp. 852
Author(s):  
Jong Hyeok Oh ◽  
Yun Seop Yu
Keyword(s):  
Integrated Circuit ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Electrical Coupling ◽  
Propagation Delay ◽  
Channel Length ◽  
Memory Window ◽  
Switching Voltage ◽  
Logic Device

The optimal structure and process for the feedback field-effect transistor (FBFET) to operate as a logic device are investigated by using a technology computer-aided design mixed-mode simulator. To minimize the memory window of the FBFET, the channel length (Lch), thickness of silicon body (Tsi), and doping concentration (Nch) of the channel region below the gate are adjusted. As a result, the memory window increases as Lch and Tsi increase, and the memory window is minimum when Nch is approximately 9 × 1019 cm−3. The electrical coupling between the top and bottom tiers of a monolithic 3-dimensional inverter (M3DINV) consisting of an n-type FBFET located at the top tier and a p-type FBFET located at the bottom tier is also investigated. In the M3DINV, we investigate variation of switching voltage with respect to voltage transfer characteristics (VTC), with different thickness values of interlayer dielectrics (TILD), Tsi, Lch, and Nch. The variation of propagation delay of the M3DINV with different TILD, Tsi, Lch, and Nch is also investigated. As a result, the electrical coupling between the stacked FBFETs by TILD can be neglected. The switching voltage gaps increase as Lch and Tsi increase and decrease, respectively. Furthermore, the slopes of VTC of M3DINV increase as Tsi and Nch increase. For transient response, tpHL decrease as Lch, Tsi, and Nch increase, but tpLH increase as Lch and Tsi increase and it is almost the same for Nch.

Stability- and Crosstalk-Based Performance of Multi- and Double-walled Mixed CNT Bundles as Interconnect for Next-Generation Technology Nodes

2021 ◽  
Author(s):  
Gurleen Dhillon ◽  
Karmjit Singh Sandha
Keyword(s):  
Carbon Nanotube ◽  
Integrated Circuit ◽  
Promising Result ◽  
Propagation Delay ◽  
Multi Walled Carbon Nanotube ◽  
The Stability ◽  
Power Delay Product ◽  
Dissipation Power ◽  
Technology Nodes ◽  
Transmission Line Models

The temperature-dependent modeling technique (in the temperature range of 200–500[Formula: see text]K) for a mixed class of carbon nanotube (CNT) bundle interconnects is proposed. The equivalent single conductor (ESC) transmission line models of multi-walled carbon nanotube (MWCNT) and double-walled carbon nanotube (DWCNT) are combined to develop multiple single conductor (MSC) model of mixed CNT interconnects. Various possible arrangements of densely packed MWCNT and DWCNT bundles (MDCB) are considered to form different types of mixed CNT bundle structures (MDCB-1, MDCB-2, MDCB-3 and MDCB-4). The integrated circuit emphasis simulation is performed and the performances of these mixed CNT bundle interconnects are investigated in terms of propagation delay (with and without crosstalk), power dissipation, power-delay product (PDP). Switching times, overshoot voltages and Nyquist plots are analyzed to check the stability of these mixed CNT structures for global interconnect length for 32-nm, 22-nm and 16-nm technology nodes. It is observed that the MDCB-1 structure yields the most promising result in all aspects for interconnect applications in the near future.

A Review on MOSFET-Like CNTFETs

2016 ◽  
Vol 4 (2) ◽  
pp. 124-129
Author(s):  
Vikash Prasad ◽  
◽  
Debaprasad Das
Keyword(s):  
Field Effect Transistor ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Channel Length ◽  
Ring Oscillator ◽  
Design Decisions ◽  
Sram Cell ◽  
Effect Transistor ◽  
Power Delay Product ◽  
Important Design

Carbon Nanotube Field Effect Transistor (CNTFET) is one of the promising devices for future nanoscale technologies. In this paper, we have studied the drain characteristics of MOSFET-like CNTFETs for different device parameters like, channel length, diameter of CNT, and number of tubes. It is shown that these device parameters can be used to make important design decisions while designing nanoelectronic circuits. A buffer and ring oscillator circuits are designed using the MOSFET-like CNTFET and propagation delay, power, and power-delay-product (PDP) values are calculated and compared with the CMOS based designs. Also, the CNTFET technology based SRAM cell is compared with CMOS technology based SRAM in term of power consumption. We have shown that CNTFET can exhibit better performance in the nanoscale regime as compared to its CMOS counterparts.

Design of hardened flip-flop using Schmitt trigger-based SEM latch in CNTFET technology

Circuit World ◽  
2020 ◽  
Vol 47 (1) ◽  
pp. 51-59
Author(s):  
Divya Madhuri Badugu ◽  
Sunithamani S. ◽  
Javid Basha Shaik ◽  
Ramesh Kumar Vobulapuram
Keyword(s):  
Integrated Circuit ◽  
Field Effect Transistors ◽  
Schmitt Trigger ◽  
Soft Error ◽  
The Novel ◽  
Flip Flop ◽  
Content Type ◽  
Performance Improvements ◽  
Power Delay Product ◽  
Error Masking

Purpose The purpose of this paper is to design novel hardened flip-flop using carbon nanotube field effect transistors (CNTFETs). Design/methodology/approach To design the proposed flip-flop, the Schmitt trigger-based soft error masking and unhardened latches have been used. In the proposed design, the novel mechanism, i.e. hysteresis property is used to enhance the hardness of the single event upset. Findings To obtain the simulation results, all the proposed circuits are extensively simulated in Hewlett simulation program with integrated circuit emphasis software. Moreover, the results of the proposed latches are compared to the conventional latches to show performance improvements. It is noted that the proposed latch shows the performance improvements up to 25.8%, 51.2% and 17.8%, respectively, in terms of power consumption, area and power delay product compared to the conventional latches. Additionally, it is observed that the simulation result of the proposed flip-flop confirmed the correctness with its respective functions. Originality/value The novel hardened flip-flop utilizing ST based SEM latch is presented. This flip-flop is significantly improves the performance and reliability compared to the existing flip-flops.

scholarly journals Semi-analytical modelling and evaluation of uniformly doped silicene nanotransistors for digital logic gates

PLoS ONE ◽  
2021 ◽  
Vol 16 (6) ◽  
pp. e0253289
Author(s):  
Mu Wen Chuan ◽  
Kien Liong Wong ◽  
Munawar Agus Riyadi ◽  
Afiq Hamzah ◽  
Shahrizal Rusli ◽  
...  
Keyword(s):  
Performance Metrics ◽  
Field Effect Transistors ◽  
Ballistic Transport ◽  
Average Power ◽  
Logic Gates ◽  
Propagation Delay ◽  
Digital Logic ◽  
Circuit Performance ◽  
Output Terminal ◽  
Power Delay Product

Silicene has attracted remarkable attention in the semiconductor research community due to its silicon (Si) nature. It is predicted as one of the most promising candidates for the next generation nanoelectronic devices. In this paper, an efficient non-iterative technique is employed to create the SPICE models for p-type and n-type uniformly doped silicene field-effect transistors (FETs). The current-voltage characteristics show that the proposed silicene FET models exhibit high on-to-off current ratio under ballistic transport. In order to obtain practical digital logic timing diagrams, a parasitic load capacitance, which is dependent on the interconnect length, is attached at the output terminal of the logic circuits. Furthermore, the key circuit performance metrics, including the propagation delay, average power, power-delay product and energy-delay product of the proposed silicene-based logic gates are extracted and benchmarked with published results. The effects of the interconnect length to the propagation delay and average power are also investigated. The results of this work further envisage the uniformly doped silicene as a promising candidate for future nanoelectronic applications.

Voltage scaling – a novel approach for crosstalk reduction in global VLSI interconnects

2007 ◽  
Vol 24 (1) ◽  
pp. 40-45 ◽  
Author(s):  
B.K. Kaushik ◽  
S. Sarkar ◽  
R.P. Agarwal ◽  
R.C. Joshi
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Reducing Power ◽  
Propagation Delay ◽  
Voltage Scaling ◽  
Content Type ◽  
New Era ◽  
Novel Approach ◽  
Crosstalk Reduction ◽  
Power Delay Product

PurposeTo analyze the effect of voltage scaling on crosstalk.Design/methodology/approachVoltage scaling has been often used for reducing power dissipation of CMOS driven interconnects. An undesired effect observed due to voltage scaling is increase in propagation delay. Thus, a trade off lies between power dissipation and propagation delay with voltage scaling. However, voltage scaling can result in overall reduction of power delay product. Therefore, their lies an optimized supply voltage where‐in power dissipation and propagation delay can be optimized. Many of the previous researches have discussed about power dissipation and propagation delay only with voltage scaling. This paper for first time shows the effect on crosstalk in voltage scaled interconnects. In this paper, we primarily study the noise for an input signal having transition time of 50 ps. The simulations are run for interconnect length of 2 and 4 mm. These parameters are varied for four different cases of stimulations to aggressor and victim lines viz. VA (input at aggressor node A) and VB (input at victim node B) switching in same direction; VA is switching and VB at static low; VA and VB are switching in opposite direction; VA is switching and VB at static high.FindingsIt is quite encouraging to observe that irrespective of interconnect length and technology node used, an optimized voltage scaling reduces normalized crosstalk level.Originality/valueVoltage scaling can be effectively used for crosstalk reduction by the new era VLSI interconnect designers. This paper shows simulation results for crosstalk reduction in different nano‐sized CMOS driven RLC‐modeled interconnects.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

scholarly journals Impact of device scaling on the electrical properties of MoS2 field-effect transistors

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Goutham Arutchelvan ◽  
Quentin Smets ◽  
Devin Verreck ◽  
Zubair Ahmed ◽  
Abhinav Gaur ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
Oxide Thickness ◽  
Channel Length ◽  
Contact Length ◽  
Power Performance ◽  
Semiconducting Materials ◽  
Large Area ◽  
Short Channel ◽  
Device Scaling ◽  
Performance Area

AbstractTwo-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.

Fusion based learning approach for predicting concrete pouring productivity based on construction and supply parameters

2016 ◽  
Vol 16 (2) ◽  
pp. 185-202 ◽  
Author(s):  
Mojtaba Maghrebi ◽  
Ali Shamsoddini ◽  
S. Travis Waller
Keyword(s):  
Supply Chain ◽  
Production Rate ◽  
Learning Method ◽  
Data Set ◽  
Content Type ◽  
Field Database ◽  
The Stability ◽  
Stable Learning ◽  
Ready Mixed Concrete ◽  
Practical Implications

Purpose The purpose of this paper is to predict the concrete pouring production rate by considering both construction and supply parameters, and by using a more stable learning method. Design/methodology/approach Unlike similar approaches, this paper considers not only construction site parameters, but also supply chain parameters. Machine learner fusion-regression (MLF-R) is used to predict the production rate of concrete pouring tasks. Findings MLF-R is used on a field database including 2,600 deliveries to 507 different locations. The proposed data set and the results are compared with ANN-Gaussian, ANN-Sigmoid and Adaboost.R2 (ANN-Gaussian). The results show better performance of MLF-R obtaining the least root mean square error (RMSE) compared with other methods. Moreover, the RMSEs derived from the predictions by MLF-R in some trials had the least standard deviation, indicating the stability of this approach among similar used approaches. Practical implications The size of the database used in this study is much larger than the size of databases used in previous studies. It helps authors draw their conclusions more confidently and introduce more generalised models that can be used in the ready-mixed concrete industry. Originality/value Introducing a more stable learning method for predicting the concrete pouring production rate helps not only construction parameters, but also traffic and supply chain parameters.

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