A Design of Power-Efficient AES Algorithm on Artix-7 FPGA for Green Communication

2021 ◽  
Author(s):  
Keshav Kumar ◽  
Amanpreet Kaur ◽  
K. R. Ramkumar ◽  
Anurag Shrivastava ◽  
Vishal Moyal ◽  
...  
Keyword(s):  
Green Communication ◽  
Power Efficient ◽  
Aes Algorithm

Very Compact and Efficient 32-Bit AES Core Design Using FPGAs for Small-Footprint Low-Power Embedded Applications

2016 ◽  
Vol 25 (07) ◽  
pp. 1650080 ◽  
Author(s):  
Raed Bani-Hani ◽  
Khaldoon Mhaidat ◽  
Salah Harb
Keyword(s):  
Low Power ◽  
Area Ratio ◽  
Advanced Encryption Standard ◽  
Fpga Design ◽  
Power Efficient ◽  
Aes Algorithm ◽  
Lookup Tables ◽  
Small Footprint ◽  
Embedded Applications

In this paper, a very compact and efficient 32-bit FPGA design for the Advanced Encryption Standard (AES) algorithm is presented. The design is very well suited for small foot-print low-power embedded applications. The design is validated and synthesized using the Xilinx ISE Design Suite. To the best of our knowledge, our design is the most efficient in terms of throughput to area ratio and requires the smallest number of lookup tables (LUTs), logic slices, and registers. It also achieves the highest throughput among designs that do not use DSPs. It is also very power-efficient; it can process more than 10 Gbps/W on Kintex-7 FPGA.

scholarly journals Design of Energy Efficient Control Unit and Implementation on High Performance FPGA

2019 ◽  
Vol 8 (12S2) ◽  
pp. 23-26
Keyword(s):  
Power Consumption ◽  
Energy Efficient ◽  
Field Programmable Gate Array ◽  
High Performance ◽  
Control Unit ◽  
Input Output ◽  
Green Communication ◽  
Power Efficient ◽  
Efficient Control ◽  
Field Programmable

With the crisis of power across the globe, green communication and power-efficient devices are getting more and more attention. This work emphasis about the implementation of Control Unit (CU) circuit on FPGA kit. In this project, power consumption of CU circuit is analyzed by changing the different Input/Output (I/O) standards of FPGA. This project is implemented on Xilinx 14.1 tool and the power consumption on CU is calculated with X Power Analyzer tool on 28-Nano-Meter (nm) Artix-7 Field Programmable Gate Array (FPGA). Out of different I/O standards, CU circuit is most power efficient with LVCMOS I/O standard on Artix-7 FPGA

scholarly journals Power Efficient Model of PWM Generator for Green Computing and Communication on High Performance FPGAs

2021 ◽  
Author(s):  
Keshav Kumar ◽  
Bishwajeet Pandey
Keyword(s):  
High Performance ◽  
Average Power ◽  
Green Computing ◽  
Communication Model ◽  
Main Function ◽  
Green Communication ◽  
Power Efficient ◽  
Power And Energy ◽  
20 Nm ◽  
28 Nm

Abstract PWM generator is one of the core modules of a communication model. Its main function is to control the amplitude of signal and used for reducing average power of the pulses and signals. The PWM generator can also be used in promoting the green computing and green communication other than data and wireless communication if it is made power and energy efficient. In this work we are using different Stub Series Terminated Logic (SSTL) IO with three distinguished FPGAs of different Nano meter (nm) gate size that are 28 nm SPARTAN-7, 20 nm KINTEX-7 Ultra scale, and 16 nm ZYNQ Ultra scale+. The model has been synthesized and implemented on VIVADO ISE tool. From the power analysis it is observed that 16 nm ZYNQ Ultra scale+ requires the highest amount of power for operation with SSTL18_I IO and 28 nm SPARTAN-7 uses least amount of power for the operation with SSTL135 IO, while the 20 nm KINTEX-7 Ultra scale lies in mid of both of these devices.

scholarly journals Design of Energy Efficient Control Unit and Implementation on High Performance FPGA

2019 ◽  
Vol 8 (12S2) ◽  
pp. 23-26
Keyword(s):  
Power Consumption ◽  
Energy Efficient ◽  
Field Programmable Gate Array ◽  
High Performance ◽  
Control Unit ◽  
Input Output ◽  
Green Communication ◽  
Power Efficient ◽  
Efficient Control ◽  
Field Programmable

With the crisis of power across the globe, green communication and power-efficient devices are getting more and more attention. This work emphasis about the implementation of Control Unit (CU) circuit on FPGA kit. In this project, power consumption of CU circuit is analyzed by changing the different Input/Output (I/O) standards of FPGA. This project is implemented on Xilinx 14.1 tool and the power consumption on CU is calculated with X Power Analyzer tool on 28-Nano-Meter (nm) Artix-7 Field Programmable Gate Array (FPGA). Out of different I/O standards, CU circuit is most power efficient with LVCMOS I/O standard on Artix-7 FPGA.

scholarly journals VLSI Implementation of Green Computing Control Unit on Zynq FPGA for Green Communication

2021 ◽  
Vol 2021 ◽  
pp. 1-10
Author(s):  
Anurag Shrivastava ◽  
Ali Rizwan ◽  
Neelam Sanjeev Kumar ◽  
R. Saravanakumar ◽  
Inderjit Singh Dhanoa ◽  
...  
Keyword(s):  
Power Consumption ◽  
Control Unit ◽  
Total Power ◽  
Processing Unit ◽  
Clock Frequency ◽  
Green Communication ◽  
Green Networking ◽  
Power Efficient ◽  
Total Power Consumption ◽  
5 Ghz

The issue of the energy shortage is affecting the entire planet. This is occurring because of massive population and industry growth around the world. As a result, the entire world is attempting to implement green networking systems and manufacture the power/energy efficient products. This research work discusses the green networking system technologies. This work introduces a power-efficient control unit (CU) design and implemented on the Zynq SoC (System on Chip) ultrascale field programmable gate array (FPGA). The VIVADO HLx Design Suite is used to simulate and analyze the CU model which is considered as one of the key components of central processing unit (CPU), used for data communication purposes. The CU is made suitable for the green communication by making it power-efficient. Therefore, the power consumption of the CU is analyzed for the various set frequency value ranging between 100 MHz and 5 GHz, and it is discovered that as the clock frequency rises up, the total power consumption also tends to get increased. The total power of the proposed model is reduced by 77.42%, 21.29%, and 17.93% from three models, respectively, being compared in the present paper. Final results shows that the CU is better suited to run at low frequencies to optimize power consumption.

Fast Pipelined Aes Algorithm Implemented on Xilinx Fpgas

2012 ◽  
Vol 2 (10) ◽  
pp. 1-4
Author(s):  
Raj Koti D Raj Koti D ◽  
◽  
Manoj Varma P Manoj Varma P
Keyword(s):  
Aes Algorithm
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