Architecture and memory requirements for stand-alone and hierarchical MPEG2 HDTV-decoders with synchronous DRAMs

Proceedings of ISCAS'95 - International Symposium on Circuits and Systems ◽

10.1109/iscas.1995.521587 ◽

2002 ◽

Author(s):

M. Winzker ◽

P. Pirsch ◽

J. Reimers

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