Influence of gain saturation on the tuning range and tuning rate of three-contact DFB lasers and amplifier-filters: modelling and experiments

Author(s):  
H. Nakajima ◽  
J. Charil ◽  
S. Slempkes ◽  
A. Gloukhian ◽  
D. Robein ◽  
...  
Author(s):  
Shitesh Tiwari ◽  
Sumant Katiyal ◽  
Parag Parandkar

Voltage Controlled Oscillator (VCO) is an integral component of most of the receivers such as GSM, GPS etc. As name indicates, oscillation is controlled by varying the voltage at the capacitor of LC tank. By varying the voltage, VCO can generate variable frequency of oscillation. Different VCO Parameters are contrasted on the basis of phase noise, tuning range, power consumption and FOM. Out of these phase noise is dependent on quality factor, power consumption, oscillation frequency and current. So, design of LC VCO at low power, low phase noise can be obtained with low bias current at low voltage.  Nanosize transistors are also contributes towards low phase noise. This paper demonstrates the design of low phase noise LC VCO with 4.89 GHz tuning range from 7.33-11.22 GHz with center frequency at 7 GHz. The design uses 32nm technology with tuning voltage of 0-1.2 V. A very effective Phase noise of -114 dBc / Hz is obtained with FOM of -181 dBc/Hz. The proposed work has been compared with five peer LC VCO designs working at higher feature sizes and outcome of this performance comparison dictates that the proposed work working at better 32 nm technology outperformed amongst others in terms of achieving low Tuning voltage and moderate FoM, overshadowed by a little expense of power dissipation. 


PIERS Online ◽  
2008 ◽  
Vol 4 (4) ◽  
pp. 433-436 ◽  
Author(s):  
Yaping Liang ◽  
Calvin W. Domier ◽  
Neville C. Luhmann, Jr.

1988 ◽  
Vol 24 (16) ◽  
pp. 988 ◽  
Author(s):  
J. Mellis ◽  
S.A. Al-Chalabi ◽  
K.H. Cameron ◽  
R. Wyatt ◽  
J.C. Regnault ◽  
...  

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Denis V. Novitsky ◽  
Dmitry Lyakhov ◽  
Dominik Michels ◽  
Dmitrii Redka ◽  
Alexander A. Pavlov ◽  
...  

AbstractUnique and flexible properties of non-Hermitian photonic systems attract ever-increasing attention via delivering a whole bunch of novel optical effects and allowing for efficient tuning light-matter interactions on nano- and microscales. Together with an increasing demand for the fast and spatially compact methods of light governing, this peculiar approach paves a broad avenue to novel optical applications. Here, unifying the approaches of disordered metamaterials and non-Hermitian photonics, we propose a conceptually new and simple architecture driven by disordered loss-gain multilayers and, therefore, providing a powerful tool to control both the passage time and the wave-front shape of incident light with different switching times. For the first time we show the possibility to switch on and off kink formation by changing the level of disorder in the case of adiabatically raising wave fronts. At the same time, we deliver flexible tuning of the output intensity by using the nonlinear effect of loss and gain saturation. Since the disorder strength in our system can be conveniently controlled with the power of the external pump, our approach can be considered as a basis for different active photonic devices.


Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 889
Author(s):  
Xiaoying Deng ◽  
Peiqi Tan

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.


Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1382
Author(s):  
Xiaoying Deng ◽  
Huazhang Li ◽  
Mingcheng Zhu

Based on the idea of bisection method, a new structure of All-Digital Phased-Locked Loop (ADPLL) with fast-locking is proposed. The structure and locking method are different from the traditional ADPLLs. The Control Circuit consists of frequency compare module, mode-adjust module and control module, which is responsible for adjusting the frequency control word of digital-controlled-oscillator (DCO) by Bisection method according to the result of the frequency compare between reference clock and restructure clock. With a high frequency cascade structure, the DCO achieves wide tuning range and high resolution. The proposed ADPLL was designed in SMIC 180 nm CMOS process. The measured results show a lock range of 640-to-1920 MHz with a 40 MHz reference frequency. The ADPLL core occupies 0.04 mm2, and the power consumption is 29.48 mW, with a 1.8 V supply. The longest locking time is 23 reference cycles, 575 ns, at 1.92 GHz. When the ADPLL operates at 1.28 GHz–1.6 GHz, the locking time is the shortest, only 9 reference cycles, 225 ns. Compared with the recent high-performance ADPLLs, our design shows advantages of small area, short locking time, and wide tuning range.


Author(s):  
Titus Oyedokun ◽  
Riana H. Geschke ◽  
Tinus Stander

Abstract We present a tunable planar groove gap waveguide (PGGWG) resonant cavity at Ka-band. The cavity demonstrates varactor loading and biasing without bridging wires or annular rings, as commonly is required in conventional substrate-integrated waveguide (SIW) resonant cavities. A detailed co-simulation strategy is also presented, with indicative parametric tuning data. Measured results indicate a 4.48% continuous frequency tuning range of 32.52–33.98 GHz and a Qu tuning range of 63–85, corresponding to the DC bias voltages of 0–16 V. Discrepancies between simulated and measured results are analyzed, and traced to process variation in the multi-layer printed circuit board stack, as well as unaccounted varactor parasitics and surface roughness.


Author(s):  
Quoc Hung Dang ◽  
Shengjian Jammy Chen ◽  
Damith Chinthana Ranasinghe ◽  
Christophe Fumeaux
Keyword(s):  

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