CODESL: A Framework for System-Level Modelling, Co-simulation and Design-Space Exploration of Embedded Systems Based on System-on-Chip

2010 ◽  
Author(s):  
Y. W. Hau ◽  
Mohamed Khalil-Hani ◽  
M. N. Marsono
Keyword(s):  
Embedded Systems ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
System On Chip ◽  
System Level ◽  
On Chip

scholarly journals Towards a design space exploration methodology for system-on-chip

2014 ◽  
Vol 14 (1) ◽  
pp. 101-111
Author(s):  
A. Chariete ◽  
M. Bakhouya ◽  
J. Gaber ◽  
M. Wack
Keyword(s):  
Feedback Control ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
System On Chip ◽  
Congestion Avoidance ◽  
Chip Design ◽  
Traffic Pattern ◽  
The Third ◽  
On Chip

Abstract This paper provides an overview of a design space exploration methodology for customizing or tuning a candidate OCI architecture, given a resources budget and independent of a particular application traffic pattern. Three main approaches are introduced. The first approach allows customizing the On- Chip Interconnect by adding strategic long-rang links, while the second consists in customizing the buffer sizes at each switch according to the traffic. The third approach uses a feedback control-based mechanism for dynamic congestion avoidance. Some results are presented to shed more light on the usefulness of these approaches for System-on-Chip design.

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