Design and Performance of Low-Power, High-Speed, Polarization-Independent and Wideband Polymer Buried-Channel Waveguide Thermo-Optic Switches

2014 ◽  
Vol 32 (17) ◽  
pp. 3067-3073 ◽  
Author(s):  
Nan Xie ◽  
Takafumi Hashimoto ◽  
Katsuyuki Utaka
Keyword(s):  
Low Power ◽  
High Speed ◽  
Channel Waveguide ◽  
Buried Channel ◽  
And Performance ◽  
Polarization Independent

scholarly journals Carrier Transport in High-Mobility III–V Quantum-Well Transistors and Performance Impact for High-Speed Low-Power Logic Applications

2008 ◽  
Vol 29 (10) ◽  
pp. 1094-1097 ◽  
Author(s):  
G. Dewey ◽  
M.K. Hudait ◽  
Kangho Lee ◽  
R. Pillarisetty ◽  
W. Rachmady ◽  
...  
Keyword(s):  
Quantum Well ◽  
Low Power ◽  
High Speed ◽  
Carrier Transport ◽  
High Mobility ◽  
Performance Impact ◽  
And Performance ◽  
Low Power Logic

A low-power and high-speed submicron buried-channel MOSFET fabricated on the buried oxide

1982 ◽  
Vol 29 (8) ◽  
pp. 1331-1332 ◽  
Author(s):  
Y. Omura ◽  
E. Sano ◽  
K. Ohwada ◽  
K. Hirata ◽  
Y. Sakakibara
Keyword(s):  
Low Power ◽  
High Speed ◽  
Buried Oxide ◽  
Buried Channel

scholarly journals Design and Implementation of High Speed and Low Power 12-bit SAR ADC using 22nm FinFET

2022 ◽  
Vol 17 ◽  
pp. 1-15
Author(s):  
G. Vasudeva ◽  
B. V. Uma
Keyword(s):  
Low Power ◽  
High Speed ◽  
Performance Metrics ◽  
Sampling Rate ◽  
Geometrical Parameters ◽  
Design Strategies ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Transconductance Amplifier ◽  
And Performance

Successive Approximation Register (SAR) Analog to Digital Converter (ADC) architecture comprises of sub modules such as comparator, Digital to Analog Converter and SAR logic. Each of these modules imposes challenges as the signal makes transition from analog to digital and vice-versa. Design strategies for optimum design of circuits considering 22nm FinFET technology meeting area, timing, power requirements and ADC metrics is presented in this work. Operational Transconductance Amplifier (OTA) based comparator, 12-bit two stage segmented resistive string DAC architecture and low power SAR logic is designed and integrated to form the ADC architecture with maximum sampling rate of 1 GS/s. Circuit schematic is captured in Cadence environment with optimum geometrical parameters and performance metrics of the proposed ADC is evaluated in MATLAB environment. Differential Non Linearity and Integral Non Linearity metrics for the 12-bit ADC is limited to +1.15/-1 LSB and +1.22/-0.69 LSB respectively. ENOB of 10.1663 with SNR of 62.9613 dB is achieved for the designed ADC measured for conversion of input signal of 100 MHz with 20dB noise. ADC with sampling frequency upto 1 GSps is designed in this work with low power dissipation less than 10 mW.

scholarly journals Design and Performance Analysis of Low Power High Speed 4x4 CNTFET Binary Content Addressable Memory Array

2019 ◽  
Vol 9 (1) ◽  
pp. 5962-5965
Keyword(s):  
Performance Analysis ◽  
Low Power ◽  
High Speed ◽  
Peak Power ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Content Addressable Memory ◽  
Power Peak ◽  
And Performance

In this paper, Carbon Nanotube Field Effect Transistor (CNTFET) based Binary Content Addressable Memory (BCAM) array is presented. The CAM array comprises of address decoders, encoders, data drivers and BCAM cells. Performance analysis is carried for 4X4 BCAM array. Each BCAM cell is designed based on adiabatic logic with optimum CNTFET parameter for low power and high speed applications. The performance of proposed BCAM array is analyzed for average power, peak power and search delay. The proposed CNTFET based BCAM array show improvement in the performance compared to that of complementary metal oxide semiconductor (CMOS) based BCAM array. The average power and peak power of the proposed 4x4 CNTFET BCAM array are in the range of micro watt (µW) while it is in the range of milli watt (mW) for CMOS based BCAM array. The search delay of the proposed 4X4 CNTFET BCAM array is improved by 32.3% compared to that of CMOS based BCAM array. All simulations are conducted for both CNTFET and CMOS based BCAM cells, BCAM array in HSPICE at 32 nm technology.

scholarly journals Design and Performance Analysis of Low Power High Speed Adder and Multiplier Using MTCMOS in 90nm, 70nm, 25nm and 18nm Regime

2021 ◽  
Author(s):  
Kalpana.K ◽  
Paulchamy. B ◽  
Priyadharsini. R ◽  
Arun Kumar Sivaraman ◽  
Rajiv Vincent ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Arithmetic Operation ◽  
Low Power Consumption ◽  
Vlsi Technology ◽  
And Performance ◽  
System Designs ◽  
Speed Propagation ◽  
Low Power Multiplier ◽  
Logic Unit

Nowadays, VLSI technology mainly focused on High-Speed Propagation and Low Power Consumption. Addition is an important arithmetic operation which plays a major role in digital application. Adder is act as an important role in the applications of signal processing, in memory access address generation and Arithmetic Logic Unit. When the number of transistors increases in system designs, makes to increase power and complexity of the circuit. One of the dominant factors is power reduction in low power VLSI technology and to overcome the power dissipation in the existing adder circuit, MTCMOS technique is used in the proposed adder. The design is simulated in 90nm, 70nm, 25nm and 18nm technology and then comparison is made between existing and proposed system in the context of energy, area and delay. In this comparison, the efficiency metrics power and delay are found to be reduced 20% from the existing adder and the proposed adder is used for the design of low power multiplier.

scholarly journals Design and Performance Analysis of Low Power High Speed CNTFET Binary Content Addressable Memory Cell for Next Generation Communication Networks

2019 ◽  
Vol 9 (2) ◽  
pp. 8-15
Keyword(s):  
Low Power ◽  
Communication Networks ◽  
High Speed ◽  
Average Power ◽  
Memory Cell ◽  
Dielectric Materials ◽  
Content Addressable Memory ◽  
Adiabatic Logic ◽  
Effect Transistor ◽  
And Performance

In this paper, Carbon Nanotube Field Effect Transistor (CNTFET) based Binary Content Addressable Memory (BCAM) cells are proposed. The adiabatic logic is integrated with the proposed BCAM cells to improve performance. The performance of proposed BCAM cells is presented for various CNTFET parameters such as number of tubes, chirality vector, pitch value, dielectric constant and dielectric materials. It also explores the optimum set of CNTFET parameters for low power and high speed characteristics of the proposed BCAM cells. Simulation results show an improvement in the average power and delay of proposed BCAM cells. The average power of the proposed BCAM cells is in the order of nano watts while the CMOS based BCAM cells is in the order of micro watts. The delay of the proposed BCAM cells is improved by 56.4 %. All simulations are conducted for both CMOS and CNTFET based BCAM cells in HSPICE at 32 nm technology

Model and performance of hot-electron MOS transistors for high-speed, low power LSI

1978 ◽  
Author(s):  
B. Hoefflinger ◽  
H. Sibbert ◽  
G. Zimmer ◽  
E. Kubalek ◽  
E. Menzel
Keyword(s):  
Low Power ◽  
High Speed ◽  
Hot Electron ◽  
Mos Transistors ◽  
And Performance
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