On estimation of static power-peformance in TCAM

2008 ◽  
Author(s):  
Dhireesha Kudithipudi ◽  
Eugene John
Keyword(s):  
Static Power

Design for Test and Diagnosis of Power Switches

2015 ◽  
Vol 25 (03) ◽  
pp. 1640013
Author(s):  
Miroslav Valka ◽  
Alberto Bosio ◽  
Luigi Dilillo ◽  
Patrick Girard ◽  
Arnaud Virazel ◽  
...  
Keyword(s):  
Power Consumption ◽  
Industrial Test ◽  
Design For Test ◽  
Power Gating ◽  
Test Quality ◽  
Worst Case ◽  
Manufacturing Defects ◽  
Efficient Test ◽  
Power Switches ◽  
Static Power

Power gating techniques have been adopted so far to reduce the static power consumption of integrated circuits (ICs). Power gating is usually implemented by means of several power switches (PSs). Manufacturing defects affecting PSs can lead to increase in the actual static power consumption and, in the worst case, they can completely isolate a functional block in the IC. Thus, efficient test and diagnosis solutions are needed. In this paper, we present a novel Design for Test and Diagnosis (DfTD) solution able to increase the test quality and diagnosis accuracy of PSs. The proposed approach has been validated through SPICE simulations on ITC’99 benchmark circuits as well as on industrial test cases.

scholarly journals ZTC bias point of advanced fin based device: The importance and exploration

2015 ◽  
Vol 28 (3) ◽  
pp. 393-405 ◽  
Author(s):  
Sushanta Mohapatra ◽  
Kumar Pradhan ◽  
Prasanna Sahu
Keyword(s):  
Power Dissipation ◽  
Temperature Compensation ◽  
Performance Metrics ◽  
Zero Temperature ◽  
Sweet Spot ◽  
Static Power ◽  
20 Nm ◽  
Bias Point ◽  
The Impact ◽  
Present Understanding

The present understanding of this work is about to evaluate and resolve the temperature compensation point (TCP) or zero temperature coefficient (ZTC) point for a sub-20 nm FinFET. The sensitivity of geometry parameters on assorted performances of Fin based device and its reliability over ample range of temperatures i.e. 25?C to 225?C is reviewed to extend the benchmark of device scalability. The impact of fin height (HFin), fin width (WFin), and temperature (T) on immense performance metrics including on-off ratio (Ion/Ioff), transconductance (gm), gain (AV), cut-off frequency (fT), static power dissipation (PD), energy (E), energy delay product (EDP), and sweet spot (gmfT/ID) of the FinFET is successfully carried out by commercially available TCAD simulator SentaurusTM from Synopsis Inc.

scholarly journals Countermeasures against Static Power Attacks

2021 ◽  
pp. 780-805
Author(s):  
Thorben Moos ◽  
Amir Moradi
Keyword(s):  
Process Variations ◽  
Cost Effective ◽  
Design Flow ◽  
Sensitive Information ◽  
Standard Cell ◽  
Aging Effects ◽  
Cell Library ◽  
Effective Option ◽  
Static Power ◽  
Power Attacks

In recent years it has been demonstrated convincingly that the standby power of a CMOS chip reveals information about the internally stored and processed data. Thus, for adversaries who seek to extract secrets from cryptographic devices via side-channel analysis, the static power has become an attractive quantity to obtain. Most works have focused on the destructive side of this subject by demonstrating attacks. In this work, we examine potential solutions to protect circuits from silently leaking sensitive information during idle times. We focus on countermeasures that can be implemented using any common digital standard cell library and do not consider solutions that require full-custom or analog design flow. In particular, we evaluate and compare a set of five distinct standard-cell-based hiding countermeasures, including both, randomization and equalization techniques. We then combine the hiding countermeasures with state-of-the-art hardware masking in order to amplify the noise level and achieve a high resistance against attacks. An important part of our contribution is the proposal and evaluation of the first ever standard-cell-based balancing scheme which achieves perfect data-independence on paper, i.e., in absence of intra-die process variations and aging effects. We call our new countermeasure Exhaustive Logic Balancing (ELB). While this scheme, applied to a threshold implementation, provides the highest level of resistance in our experiments, it may not be the most cost effective option due to the significant resource overhead associated. All evaluated countermeasures and combinations thereof are applied to a serialized hardware implementation of the PRESENT block cipher and realized as cryptographic co-processors on a 28nm CMOS ASIC prototype. Our experimental results are obtained through real-silicon measurements of a fabricated die of the ASIC in a temperature-controlled environment using a source measure unit (SMU). We believe that our elaborate comparison serves as a useful guideline for hardware designers to find a proper tradeoff between security and cost for almost any application.

scholarly journals A Flux Controlled Memristor using 90nm Technology

2021 ◽  
pp. 1-6
Author(s):  
B.T. Krishna ◽  
◽  
Shaik. mohaseena Salma ◽  
Keyword(s):  
Power Supply ◽  
Power Dissipation ◽  
Power Efficiency ◽  
Current Mode ◽  
Cmos Technology ◽  
Theoretical Simulation ◽  
Transconductance Amplifier ◽  
Higher Power ◽  
Static Power ◽  
A Current

A flux-controlled memristor using complementary metal–oxide–(CMOS) structure is presented in this study. The proposed circuit provides higher power efficiency, less static power dissipation, lesser area, and can also reduce the power supply by using CMOS 90nm technology. The circuit is implemented based on the use of a second-generation current conveyor circuit (CCII) and operational transconductance amplifier (OTA) with few passive elements. The proposed circuit uses a current-mode approach which improves the high frequency performance. The reduction of a power supply is a crucial aspect to decrease the power consumption in VLSI. An offered emulator in this proposed circuit is made to operate incremental and decremental configurations well up to 26.3 MHZ in cadence virtuoso platform gpdk using 90nm CMOS technology. proposed memristor circuit has very little static power dissipation when operating with ±1V supply. Transient analysis, memductance analysis, and dc analysis simulations are verified practically with the Experimental demonstration by using ideal memristor made up of ICs AD844AN and CA3080, using multisim which exhibits theoretical simulation are verified and discussed.

scholarly journals Design of low power 8-bit gate-diffusion input (GDI) full adder using variable body bias (VBB) technique in 90nm technology

2019 ◽  
Vol 14 (2) ◽  
pp. 912
Author(s):  
Woo Wei Kai ◽  
Nabihah Ahmad ◽  
Mohamad Hairol Jabbar
Keyword(s):  
Low Power ◽  
Average Power ◽  
Full Adder ◽  
Oxide Thickness ◽  
Low Complexity ◽  
Operating Voltage ◽  
Short Channel ◽  
Static Power ◽  
Subthreshold Leakage ◽  
Power Delay Product

In digital system, the full adders are fundamental circuits that are used for arithmetic operations. Adder operation can be used to implement and perform calculation of the multipliers, subtraction, comparators, and address operation in an Arithmetic Logic Unit (ALU). The subthreshold leakage current increasing as proportional with the scaling down of oxide thickness and transistor in short channel sizes. In this paper, a Gate-diffusion Input (GDI) circuit design technique allow minimization the number of transistor while maintaining low complexity of logic design and low power realization of Variable Body Biasing (VBB) technique to reduce the static power consumption. The Silterra 90nm process design kit (PDK) was used to design 8-bit full adder with VBB technique in full custom methodology by using Synopsys Electronic Design Automation (EDA) tools. The simulation of 8-bit full adder was compared within a conventional bias technique and VBB technique with operating voltage of  supply. The result showed the reduction of VBB technique in term of peak power,  and average power,   compare with conventional bias technique. Moreover, the Power Delay Product (PDP) showed 1.29pJ in VBB technique compare with conventional bias mode 1.67pJ. The area size of 8-Bit full adder was 10μm×23μm.

scholarly journals An Efficient Power Optimized 32 bit BCD Adder Using Multi-Channel Technique

2017 ◽  
Vol 6 (02) ◽  
pp. 07-12
Author(s):  
Diksha Siddhamshittiwar
Keyword(s):  
Average Power ◽  
Full Adder ◽  
Deep Submicron ◽  
Power Reduction ◽  
Vlsi Circuits ◽  
Power Gating ◽  
Static Power ◽  
Simulation Results ◽  
Efficient Power ◽  
Standby Mode

Static power reduction is a challenge in deep submicron VLSI circuits. In this paper 28T full adder circuit, 14T full adder circuit and 32 bit power gated BCD adder using the full adders respectively were designed and their average power was compared. In existing work a conventional full adder is designed using 28T and the same is used to design 32 bit BCD adder. In the proposed architecture 14T transmission gate based power gated full adder is used for the design of 32 bit BCD adder. The leakage supremacy dissipated during standby mode in all deep submicron CMOS devices is reduced using efficient power gating and multi-channel technique. Simulation results were obtained using Tanner EDA and TSMC_180nm library file is used for the design of 28T full adder, 14T full adder and power gated BCD adder and a significant power reduction is achieved in the proposed architecture.

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