An 8.55-17.11-GHz DDS FMCW Chirp Synthesizer PLL Based on Double-Edge Zero-Crossing Sampling PD With 51.7-fs $_{rms}$ Jitter and Fast Frequency Hopping

Author(s):  
Jinhai Xiao ◽  
Ning Liang ◽  
Bingwen Chen ◽  
Maliang Liu
Sign in / Sign up

Export Citation Format

Share Document