Continuous fabrication process of nanocellulose long-fiber under electric field for strength enhancement

2021 ◽  
Author(s):  
Jaehwan Kim ◽  
Pooja S. Panicker ◽  
Hyun-Chan Kim ◽  
Dickens O. Agumba ◽  
Samia Adil ◽  
...  
Keyword(s):  
Electric Field ◽  
Fabrication Process ◽  
Strength Enhancement ◽  
Continuous Fabrication

Low On-Resistance in 4H-SiC RESURF JFETs Fabricated with Dry Process for Implantation Metal Mask

2006 ◽  
Vol 527-529 ◽  
pp. 1203-1206 ◽  
Author(s):  
Takeyoshi Masuda ◽  
Kazuhiro Fujikawa ◽  
Kaoru Shibata ◽  
Hideto Tamaso ◽  
Satoshi Hatsukawa ◽  
...  
Keyword(s):  
Electric Field ◽  
Ion Implantation ◽  
Fabrication Process ◽  
Gate Length ◽  
Electrical Characteristics ◽  
Dry Process ◽  
Metal Mask ◽  
Surface Field ◽  
Reduced Surface

We fabricated 4H-SiC lateral JFETs with a reduced surface field (RESURF) structure, which can prevent the concentration of electric field at the edge of the gate metal [1]. Previously, we reported on the 4H-SiC RESURF JFET with a gate length (LG) of 10 μm [2]. Its specific on-resistance was 50 mΩcm2, which was still high. Therefore, a Ti/W layer was used as an ion implantation mask so as to decrease the thickness of the mask and to improve an accuracy of the device process. A RESURF JFET with the gate length (LG) of 3.0 μm was fabricated, and the specific on-resistance of 6.3 mΩcm2 was obtained. In this paper, the fabrication process and the electrical characteristics of the device are described.

Fabrication of Semiconductor Nanostructures With an Atomic Force Microscope

1995 ◽  
Vol 380 ◽  
Author(s):  
E. S. Snow ◽  
P. M. Campbell
Keyword(s):  
Electric Field ◽  
Atomic Force Microscope ◽  
Semiconductor Nanostructures ◽  
Selective Etching ◽  
Device Fabrication ◽  
Fabrication Process ◽  
Local Electric Field ◽  
Nanometer Scale ◽  
Atomic Force ◽  
Resolution Limits

ABSTRACTAn AFM-based nanolithography process is described. We employ the local electric field of a metal-coated AFM tip which is operated in air to selectively oxidize regions of a H-passivated Si surface. The resulting oxide, ∼ 3 nm thick, is used as a mask for selective etching of the unoxidized regions of Si. This AFM-based fabrication process is fast, reliable, simple to perform and is well suited for device fabrication. We apply this technique to the fabrication of Si and GaAs nanostructures, as well as to the fabrication of a nanometer-scale Si side-gated transistor. In addition, we discuss the ultimate resolution limits of the technique.

Inspection and Testing of Serially Produced Pressure Vessels

2005 ◽  
Author(s):  
Ian Roberts ◽  
Guy Baylac ◽  
Erik Zeelenberg
Keyword(s):  
Pressure Vessels ◽  
Fabrication Process ◽  
Continuous Fabrication

The vast majority of applications of EN 13445-5:2002 will be for individually designed pressure vessels, but there will be a significant sector of serially produced pressure vessels, built in a continuous fabrication process to a single design. This paper presents Annex A of EN 13445-5 which addresses inspection and testing of these pressure vessels and gives the thinking and rationale behind these requirements.

Fabrication of micro/nanostructured α-Fe2O3 hollow spheres: effect of electric field on the morphological, magnetic and photocatalytic properties

RSC Advances ◽  
2016 ◽  
Vol 6 (70) ◽  
pp. 65789-65798 ◽  
Author(s):  
Rich Kant ◽  
Neetesh Kumar ◽  
Viresh Dutta
Keyword(s):  
Electric Field ◽  
Spray Pyrolysis ◽  
Hollow Spheres ◽  
Photocatalytic Properties ◽  
Dc Voltage ◽  
Continuous Fabrication

Continuous fabrication of α-Fe2O3 hollow spheres with sponge like morphology using an electric field assisted (by applying DC voltage) continuous spray pyrolysis (CoSP) technique.

SiC Trenched Schottky Diode with Step-Shaped Junction Barrier for Superior Static Performance and Large Design Window

2020 ◽  
Vol 1014 ◽  
pp. 62-67
Author(s):  
Xi Wang ◽  
Hong Bin Pu ◽  
Ji Chao Hu ◽  
Bing Liu
Keyword(s):  
Silicon Carbide ◽  
Electric Field ◽  
Numerical Simulations ◽  
Schottky Diode ◽  
Doping Concentration ◽  
Fabrication Process ◽  
Drift Region ◽  
Reverse Blocking ◽  
Static Performance ◽  
Peak Electric Field

A novel silicon carbide (SiC) trenched schottky diode with step-shaped junction barrier is proposed for superior static performance and large design window. In the proposed diode, to improve tradeoff between specific on-resistance and surface peak electric field, the shape of the trenched-junction is modified to stair-step, without extra fabrication process. To investigate the performances of the SiC step-shaped trenched junction barrier schottky (SSTJBS) diode, numerical simulations are carried out through Silvaco TCAD. The results indicate that the proposed diode can accommodate highly doped drift region with no degradation of its reverse blocking characteristic. In comparison with the conventional SiC trenched junction barrier schottky (TJBS) diode, the proposed SiC SSTJBS diode shows a larger design window of drift region doping concentration from 7.9×1015cm-3 to 9.5×1015cm-3. In the design window, the specific on-resistance and surface peak electric field can be reduced by 12.9% and 11%, respectively.

A new fabrication process for the SOI-based miniature electric field sensor

2013 ◽  
Vol 34 (8) ◽  
pp. 086005
Author(s):  
Wei Liu ◽  
Pengfei Yang ◽  
Chunrong Peng ◽  
Dongming Fang ◽  
Shanhong Xia
Keyword(s):  
Electric Field ◽  
Fabrication Process ◽  
Electric Field Sensor ◽  
Field Sensor

Design Optimization of 1.2kV 4H-SiC Trench MOSFET

2019 ◽  
Vol 963 ◽  
pp. 605-608
Author(s):  
Tian Dai ◽  
Peter M. Gammon ◽  
Vishal Ajit Shah ◽  
Xiao Deng ◽  
Michael R. Jennings ◽  
...  
Keyword(s):  
Electric Field ◽  
Design Optimization ◽  
Gate Oxide ◽  
High Electric Field ◽  
Fabrication Process ◽  
Experimental Results ◽  
Base Region ◽  
Field Stress

In a trench MOSFET structure, p+ trench bottom implant (also called p+ shielding region) is commonly used to protect the gate oxide from high electric field stress, however, if the design and fabrication process are not optimized properly, the p+ shielding region together with n-drift and the p-base region will form a parasitic JFET which severely degrades the on-state performance of the device. This paper presents this parasitic JFET effect with experimental results and the optimization work that has been done to eliminate the parasitic JFET.

scholarly journals Fabrication of voltage-gated spin Hall nano-oscillators

Nanoscale ◽  
2022 ◽  
Author(s):  
Akash Kumar ◽  
Mona Rajabali ◽  
Victor Hugo González ◽  
Mohammad Zahedinejad ◽  
Afshin Houshang ◽  
...  
Keyword(s):  
Electric Field ◽  
Fabrication Process ◽  
Voltage Gated ◽  
Voltage Gate

We demonstrate an optimized fabrication process for electric field (voltage gate) controlled nano-constriction spin Hall nano-oscillators (SHNOs), achieving feature sizes of <30 nm with easy to handle ma-N 2401 e-beam...

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