Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches

Science ◽  
2018 ◽  
Vol 361 (6400) ◽  
pp. 387-392 ◽  
Author(s):  
Chenguang Qiu ◽  
Fei Liu ◽  
Lin Xu ◽  
Bing Deng ◽  
Mengmeng Xiao ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Field Effect ◽  
Electron Density Distribution ◽  
High Performance ◽  
Room Temperature ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
State Of The Art ◽  
Electronic Devices ◽  
Electronic Switches

An efficient way to reduce the power consumption of electronic devices is to lower the supply voltage, but this voltage is restricted by the thermionic limit of subthreshold swing (SS), 60 millivolts per decade, in field-effect transistors (FETs). We show that a graphene Dirac source (DS) with a much narrower electron density distribution around the Fermi level than that of conventional FETs can lower SS. A DS-FET with a carbon nanotube channel provided an average SS of 40 millivolts per decade over four decades of current at room temperature and high device current I60 of up to 40 microamperes per micrometer at 60 millivolts per decade. When compared with state-of-the-art silicon 14-nanometer node FETs, a similar on-state current Ion is realized but at a much lower supply voltage of 0.5 volts (versus 0.7 volts for silicon) and a much steeper SS below 35 millivolts per decade in the off-state.

scholarly journals Design and Analysis of CMOS and CNTFET based Ternary Operators for Scrambling

2019 ◽  
Vol 4 (5) ◽  
pp. 575-579
Author(s):  
Gudala Konica . ◽  
Sreenivasulu Mamilla .
Keyword(s):  
Energy Efficient ◽  
Field Effect ◽  
High Performance ◽  
Digital Circuits ◽  
Performance Metrics ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Future Generations ◽  
Power Delay Product

As silicon technology scales down, it is a dominant choice to have high-performance digital circuits. As researchers investigated for high-performance digital circuits for future generations, Carbon Nanotube Field Effect Transistors (CNTFETs) is considered as the most promising technology due to their excellent current driving capability and proved to be an alternative to conventional CMOS technology. A CNTFET based energy efficient ternary operators are proposed for scrambling applications. The transistor-level implementations of operators namely Scrambling Operator1 (SOP1), Scrambling Operator2 (SOP2) and SUM operators are simulated with CMOS and CNTFET in 32 nm technology at 0.9 V supply voltage using Synopsys HSPICE. The performance metrics like Power, Delay and Power-delay product (PDP) are measured and a comparative analysis for CNTFET and CMOS technologies is carried out. The results demonstrate that CNTFET designs have better-optimized results in power, energy consumption, and reduced transistor count.

scholarly journals Growth of high-quality semiconducting tellurium films for high-performance p-channel field-effect transistors with wafer-scale uniformity

2022 ◽  
Vol 6 (1) ◽  
Author(s):  
Taikyu Kim ◽  
Cheol Hee Choi ◽  
Pilgyu Byeon ◽  
Miso Lee ◽  
Aeran Song ◽  
...  
Keyword(s):  
Field Effect ◽  
Physical Vapor Deposition ◽  
High Performance ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Three Dimensional ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Wafer Scale

AbstractAchieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm2 V−1 s−1 and an ION/OFF ratio of 5.8 × 105 with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.

scholarly journals A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator

Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 223 ◽  
Author(s):  
Yannan Zhang ◽  
Ke Han ◽  
and Jiawei Li
Keyword(s):  
Metal Oxide ◽  
Low Power ◽  
Energy Efficient ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Future Generation ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Ultra Low Power

Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices.

scholarly journals High performance p-channel transistors on flexible substrate using direct roll transfer stamping

2021 ◽  
Author(s):  
Ayoub Abdulhafith Sadek Zumeit ◽  
Abhishek S Dahiya ◽  
Adamos Christou ◽  
Ravinder Dahiya
Keyword(s):  
High Performance ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Flexible Substrate ◽  
Electronic Devices ◽  
Silicon On Insulator ◽  
Flexible Substrates ◽  
Device Performance ◽  
Mechanical Bending ◽  
P Type

Abstract lexible electronics with high-performance devices is crucial for transformative advances in several emerging and traditional applications. To address this need, herein we present p-type silicon (Si) nanoribbons (NR)-based high-performance field-effect transistors (FETs) developed using innovative Direct Roll Transfer Stamping (DRTS) process. First, ultrathin Si NRs (~70 nm) are obtained from silicon on insulator (SOI) wafers using conventional top-down method, and then DRTS method is employed to directly place the NRs onto flexible substrates at room temperature (RT). The NRFETs are then developed following RT fabrication process which include deposition of high-quality SiNx dielectric. The fabricated p-channel transistors demonstrate high linear mobility ~100±10 cm2/Vs, current on/off ratio >10^4, and low gate leakage (<1nA). Further, the transistors showed robust device performance under mechanical bending and at wide temperature range (15 to 90 °C), showing excellent potential for futuristic high-performance flexible electronic devices/circuits.

High performance electronic devices based on nanofibers via a crosslinking welding process

Nanoscale ◽  
2018 ◽  
Vol 10 (41) ◽  
pp. 19427-19434 ◽  
Author(s):  
Youchao Cui ◽  
You Meng ◽  
Zhen Wang ◽  
Chunfeng Wang ◽  
Guoxia Liu ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Epoxy Resin ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Electronic Devices ◽  
Welding Process ◽  
Device Performance ◽  
Adhesion Performance

An amine-hardened epoxy resin was selected as adhesion agent to weld nanofiber and improve the adhesion performance, resulting in low contact-resistance nanofiber networks (NFNs). The field-effect transistors based on In2O3 NFNs/SiO2 exhibit high device performance.

scholarly journals Designing a Novel High Performance Four-to-Two Compressor Cell Based on CNTFET Technology for Low Voltages

2018 ◽  
Vol 8 (6) ◽  
pp. 4863
Author(s):  
Mehdi Bagherizadeh ◽  
Mona Moradi ◽  
Mostafa Torabi
Keyword(s):  
Low Power ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
State Of The Art ◽  
Critical Path ◽  
Low Power Design ◽  
Software Simulation ◽  
Majority Function ◽  
Simulation Results

<p>Compressor cell is often placed in critical path of multiplier circuits to perform partial product summation. Therefore it plays a significant role in determining the entire performance of multiplier and digital system. Respecting to the necessity of low power design for portable electronic, designing a low power and high performance compressors seems to be a good solution to overcome of these problems for computations. In this paper a novel high performance four-to-two compressor cell is proposed using Carbon Nanotube Field Effect Transistors (CNTFETs) technology. The new cell is based on Majority Function, NOR, and NAND gates. The main advantage of proposed design in comparison with former cells is the ease of obtaining CARRY output by means of Majority function. Simulations have been done with 32nm technology node using Synopsys HSPICE software. Simulation results confirm the priority of the proposed cell compared to other state-of-the-art four-to-two compressor cells.</p>

Tunnel field-effect transistors as energy-efficient electronic switches

Nature ◽  
2011 ◽  
Vol 479 (7373) ◽  
pp. 329-337 ◽  
Author(s):  
Adrian M. Ionescu ◽  
Heike Riel
Keyword(s):  
Energy Efficient ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Electronic Switches
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