scholarly journals Performance of the ATLAS Level-1 topological trigger in Run 2

2022 ◽  
Vol 82 (1) ◽  
Author(s):  
G. Aad ◽  
B. Abbott ◽  
D. C. Abbott ◽  
A. Abed Abud ◽  
K. Abeling ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
Transverse Energy ◽  
Missing Transverse Energy ◽  
Background Event ◽  
Atlas Experiment ◽  
Field Programmable ◽  
Efficient Data ◽  
Design Value ◽  
Level 1 ◽  
Gate Array

AbstractDuring LHC Run 2 (2015–2018) the ATLAS Level-1 topological trigger allowed efficient data-taking by the ATLAS experiment at luminosities up to 2.1$$\times $$ × 10$$^{34}$$ 34  cm$$^{-2}$$ - 2 s$$^{-1}$$ - 1 , which exceeds the design value by a factor of two. The system was installed in 2016 and operated in 2017 and 2018. It uses Field Programmable Gate Array processors to select interesting events by placing kinematic and angular requirements on electromagnetic clusters, jets, $$\tau $$ τ -leptons, muons and the missing transverse energy. It allowed to significantly improve the background event rejection and signal event acceptance, in particular for Higgs and B-physics processes.

Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows

2008 ◽  
Author(s):  
Michael Wirthlin ◽  
Brent Nelson ◽  
Brad Hutchings ◽  
Peter Athanas ◽  
Shawn Bohner
Keyword(s):  
Field Programmable Gate Array ◽  
Fpga Design ◽  
Design Methodologies ◽  
Field Programmable ◽  
Gate Array

Real-time signal processing in field programmable gate array based digital gamma-ray spectrometer

2020 ◽  
Vol 91 (10) ◽  
pp. 104707
Author(s):  
Yinyu Liu ◽  
Hao Xiong ◽  
Chunhui Dong ◽  
Chaoyang Zhao ◽  
Quanfeng Zhou ◽  
...  
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
Field Programmable Gate Array ◽  
Gamma Ray ◽  
Time Signal ◽  
Gamma Ray Spectrometer ◽  
Field Programmable ◽  
Gate Array ◽  
Real Time Signal Processing

scholarly journals True Random Number Generator Based on Fibonacci-Galois Ring Oscillators for FPGA

2021 ◽  
Vol 11 (8) ◽  
pp. 3330
Author(s):  
Pietro Nannipieri ◽  
Stefano Di Matteo ◽  
Luca Baldanzi ◽  
Luca Crocetti ◽  
Jacopo Belli ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
Random Number ◽  
Random Number Generator ◽  
Random Number Generation ◽  
Galois Ring ◽  
Number Generator ◽  
True Random Number Generator ◽  
Number Generation ◽  
Field Programmable ◽  
Gate Array

Random numbers are widely employed in cryptography and security applications. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the information, breaking even the most robust implementation of a cipher. Due to their intrinsic close relationship with analogue parameters of the circuit, True Random Number Generators are usually tailored on specific silicon technology and are not easily scalable on programmable hardware, without affecting their entropy. On the other hand, programmable hardware and programmable System on Chip are gaining large adoption rate, also in security critical application, where high quality random number generation is mandatory. The work presented herein describes the design and the validation of a digital True Random Number Generator for cryptographically secure applications on Field Programmable Gate Array. After a preliminary study of literature and standards specifying requirements for random number generation, the design flow is illustrated, from specifications definition to the synthesis phase. Several solutions have been studied to assess their performances on a Field Programmable Gate Array device, with the aim to select the highest performance architecture. The proposed designs have been tested and validated, employing official test suites released by NIST standardization body, assessing the independence from the place and route and the randomness degree of the generated output. An architecture derived from the Fibonacci-Galois Ring Oscillator has been selected and synthesized on Intel Stratix IV, supporting throughput up to 400 Mbps. The achieved entropy in the best configuration is greater than 0.995.

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