Sensorless Control Strategy for BLDC Motors Based on a Type-3 Phase Locked Loop

Author(s):  
Mohamed Abbes ◽  
Souad Chebbi

This paper presents the design procedure of a high-performance sensorless control strategy for the widely used brushless DC (BLDC) motors. Generally, conventional sensorless techniques are based on detecting the zero-crossing instants (ZCP) of the back electromotives forces (back-EMFs) of the three phases. These methods, although widely adopted and marketed on an industrial level, involve many limitations such as filtering delays, difficulty to operate at low speeds and immunity against Electromagnetic Interferences (EMI). In this paper, the main objective is to develop a sensorless control technique integrally independent from the zero-crossing points of the back-EMFs. In the proposed method, a zero-delay adaptive filter was used to extract the fundamental and the quadrature components of the line-to-line voltage of the motor. Then, the Synchronous Reference Frame Phase Locked Loop (SRF-PLL) is used to estimate the electrical angle of phase-to-phase back-EMF along with the rotor speed. The conventional SRF-PLL was implemented using a second-order loop filter (type-3 PLL) in order to improve synchronization performances and for better rejection of voltage spikes induced in motor phases during commutations. The benefits of the control technique are brought to light through simulation results. An experimental prototype was designed to confirm the validity of the proposed method.

2009 ◽  
Vol 06 (02) ◽  
pp. 205-240 ◽  
Author(s):  
JUNG-YUP KIM ◽  
ILL-WOO PARK ◽  
JUN-HO OH

In this paper, dynamic stair climbing and descending are experimentally realized for a biped humanoid robot, HUBO. Currently, in addition to biped walking on the ground, other types of biped walking such as running, jogging, and stair walking (climbing and descending) have been also studied since the end of 1990. In spite of many years of research works on stair walking, it is still a challengeable topic that requires high performance of control technique. For dynamic stair walking, we designed stair climbing and descending patterns according to a known stair configuration. Next, we defined stair climbing and descending stages for a switching control strategy. In each stage, we designed and adopted several online controllers to maintain the balance. For the simplicity and easy application, the online controllers only use the force and torque signals of the force/torque sensors of the feet. Finally, the effectiveness and performance of the proposed strategy are verified through stair climbing and descending experiments of HUBO.


Author(s):  
P.N. Metange ◽  
K. B. Khanchandani

<p>This paper presents the analysis and design of high performance phase frequency detector, charge pump and loop filter circuits for phase locked loop in wireless applications. The proposed phase frequency detector (PFD) consumes only 8 µW and utilises small area. Also, at 1.8V voltage supply the maximum operation frequency of the conventional PFD is 500 MHz whereas proposed PFD is 5 GHz. Hence, highly suitable for low power, high speed and low jitter applications.  The differential charge pump uses switches using NMOS and the inverter delays for up and down signals do not generate any offset due to its fully symmetric operation. This configuration doubles the range of output voltage compliance compared to single ended charge pump. Differential stage is less sensitive to the leakage current since leakage current behaves as common mode offset with the dual output stages. All the circuits are implemented using cadence 0.18 μm CMOS Process.</p>


The performance of Conventional sensorless back-emf detection techniques for BLDC Motor is poor at low speeds, since at zero and low speeds the magnitude of back-emf is very less. This causes failure of zero crossing instant detection. This paper presents a new Sensorless Control Technique for BLDC motor drive to estimate the rotor position accurately even at zero and low speeds. A new algorithm has been developed to estimate the rotor position based on the prediction of stator flux linkages. The main advantage of the proposed technique is that the flux linkages are independent of the speed. For starting of the motor an open loop starting method was adopted. By implementing this technique the Meta heuristic digital signal control systems like PWM/ADC, PLL are avoided in order to make motor control easy and economical. To verify the accuracy of the proposed technique it is compared with existing hall sensors controlled BLDC drive operation. The validity of proposed scheme is verified through Simulation.


2020 ◽  
Vol 15 (1) ◽  
pp. 65-76
Author(s):  
N. Hemalatha ◽  
S. Nageswari

Background: Position sensorless control technique for Permanent Magnets-Brush Less Direct Current (PM-BLDC) motor drive is considered in this paper. Materials and Methods: A new estimation based on sensorless technique is proposed for PMBLDC motor. Artificial Neural Network (ANN) is aided for the purpose. Results: The inputs to the ANN are the voltages of PM-BLDC motor and it estimates the sample signals to feed Zero Crossing Point (ZCP) detection circuit. The ZCP detection circuit provides ZCP signals for commutation logic which gives the commutation sequence to power switches. In order to provide the correct sample signal to ZCP detection circuit, the ANN is well trained by Genetic Algorithm (GA). The proposed sensor less control model is implemented in MATLAB/SIMULINK working platform. Conclusion: Field Programmable Gate Array (FPGA) is used to implement the proposed method. Experimental results verify the analysis and demonstrate the advantages of the proposed method.


2012 ◽  
Vol 182-183 ◽  
pp. 587-592
Author(s):  
Hua Fang Sun ◽  
Xin Ning Liu ◽  
Xin Chen

The effect of all-digital phase-locked loop (ADPLL) digital filter parameters on the jitter is investigated in time domain, and a systematic design procedure for ADPLL is presented. The pro-posed method not only estimates the output jitter of an ADPLL, but also finds the optimal filter pa-rameter minimizing the overall ADPLL timing jitter. To verify the theoretic analysis, an ADPLL behavior model in matlab is designed. The simulation shows significant performance improvement on the timing jitter.


2004 ◽  
Vol 13 (01) ◽  
pp. 53-63 ◽  
Author(s):  
YOUNGSHIN WOO ◽  
YOUNG MIN JANG ◽  
MAN YOUNG SUNG

In this paper, we propose a phase-locked loop (PLL) with dual PFDs and a modified loop filter in which advantages of both PFDs can be combined and the trade-off between acquisition behavior and locked behavior can be achieved. By operating the appropriate PFD connected to the well-adjusted charge pump and regulating the loop bandwidth to input frequency ratio with an input divider and a modified loop filter, an unlimited error detection range, a high frequency operation, a reduced dead zone and a higher speed lock-up time can be achieved. The proposed PLL structure is designed using 1.5 μm CMOS technology with 5 V supply voltage.


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