THE INCLUSION OF FUTURE ARRIVALS AND DOWNSTREAM SETUPS INTO WAFER FABRICATION BATCH PROCESSING DECISIONS

2002 ◽  
Vol 11 (02) ◽  
pp. 149-159 ◽  
Author(s):  
LANCE SOLOMON ◽  
JOHN W. FOWLER ◽  
MICHELE PFUND ◽  
PAUL H. JENSEN
Keyword(s):  
Batch Processing ◽  
Wafer Fabrication

Optimal batching in a wafer fabrication facility using a multiproduct G/G/c model with batch processing

2002 ◽  
Vol 40 (2) ◽  
pp. 275-292 ◽  
Author(s):  
J. W. Fowler ◽  
N. Phojanamongkolkij ◽  
J. K. Cochran ◽  
D. C. Montgomery
Keyword(s):  
Batch Processing ◽  
Wafer Fabrication

Determining operating criterion of batch processing operations for wafer fabrication

2002 ◽  
Vol 21 (5) ◽  
pp. 363-379 ◽  
Author(s):  
Nipa Phojanamongkolkij ◽  
John W. Fowler ◽  
Jeffrey K. Cochran
Keyword(s):  
Batch Processing ◽  
Wafer Fabrication

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Studies on Chemical Methods to Expose Gate/Tunnel Oxide and Identification of Gate/Tunnel Oxide Defects in Wafer Fabrication

2002 ◽  
Author(s):  
Y. N. Hua ◽  
G. B. Ang ◽  
S. Redkar ◽  
Yogaspari ◽  
Wilma Richter
Keyword(s):  
Acetic Acid ◽  
Silicon Oxide ◽  
Wafer Fabrication ◽  
Chemical Methods ◽  
Advantages And Disadvantages ◽  
Different Types ◽  
Capacitor Structure ◽  
Oxide Defects ◽  
Buffer Oxide Etchant ◽  
Etch Time

Abstract In failure analysis of wafer fabrication, currently, three different types of chemical methods including 6:6:1 (Acetic Acid/HNO3/HF), NaOH and Choline are used in removing polysilicon (poly) layer and exposing the gate/tunnel oxide underneath. However, usage is limited due to their disadvantages. For example, 6:6:1 is a relatively fast etchant, but it is difficult to control the etch time and keep the oxide layer intact. Also, while using NaOH to remove poly and expose the silicon oxide, the solution needs to be heated. It is also difficult to etch a poly layer with a WSix or a CoSix silicide using NaOH. In this paper, we will discuss these 3 etchants in terms of their advantages and disadvantages. We will then introduce a new poly etchant, called HB91. HB91 is useful for removing poly to expose the gate/tunnel oxide for identification of related defects. HB91 is actually a mixture of two chemicals namely nitric acid (HNO3) and buffer oxide etchant (BOE) in a 9:1 ratio. The experimental results show that it is highly selective in poly removal with respect to the gate/tunnel oxide and is a suitable poly etchant especially for removing polysilicon with/without WSix and CoSix in the large capacitor structure. Application results of this poly etchant (HB91) will be presented.

Studies on a Failure Analysis Flow of Surface Contamination, Corrosion, and Underetch on Microchip Al Bondpads in Wafer Fabrication

2005 ◽  
Author(s):  
Hua Younan
Keyword(s):  
Failure Analysis ◽  
Galvanic Corrosion ◽  
Surface Contamination ◽  
Wafer Fabrication ◽  
Tof Sims ◽  
Corrosion Passivation

Abstract A failure analysis flow is developed for surface contamination, corrosion and underetch on microchip Al bondpads and it is applied in wafer fabrication. SEM, EDX, Auger, FTIR, XPS and TOF-SIMS are used to identify the root causes. The results from carbon related contamination, galvanic corrosion, fluorine-induced corrosion, passivation underetch and Auger bondpad monitoring will be presented. The failure analysis flow will definitely help us to select suitable methods and tools for failure analysis of Al bondpad-related issues, identify rapidly possible root causes of the failures and find the eliminating solutions at both wafer fabrication and assembly houses.

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