A formal approach for high level synthesis of linear analog systems

Proceedings of the 16th ACM Great Lakes symposium on VLSI - GLSVLSI '06 ◽

10.1145/1127908.1127987 ◽

2006 ◽

Author(s):

Soumya Pandit ◽

Chittaranjan Mandal ◽

Amit Patra

Keyword(s):

High Level Synthesis ◽

Formal Approach ◽

Linear Analog ◽

Analog Systems ◽

High Level

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Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2003.818374 ◽

2003 ◽

Vol 22 (11) ◽

pp. 1556-1568 ◽

Cited By ~ 36

Author(s):

A. Doboli ◽

R. Vemuri

Keyword(s):

High Level Synthesis ◽

Linear Analog ◽

Analog Systems ◽

High Level

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A Formal Approach to the Slack Driven Scheduling Problem in High-Level Synthesis

2005 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2005.1465915 ◽

2005 ◽

Cited By ~ 2

Author(s):

Shih-Hsu Huang ◽

Chun-Hua Cheng

Keyword(s):

High Level Synthesis ◽

Scheduling Problem ◽

Formal Approach ◽

High Level

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Library finding for high-level synthesis of analog systems

VLSI Design 2001. Fourteenth International Conference on VLSI Design ◽

10.1109/icvd.2001.902671 ◽

2002 ◽

Cited By ~ 1

Author(s):

S. Ganesan ◽

R. Vemuri

Keyword(s):

High Level Synthesis ◽

Analog Systems ◽

High Level

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A formal approach to slack-driven high-level synthesis

2012 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2012.6272098 ◽

2012 ◽

Cited By ~ 2

Author(s):

Hua-Hsin Yeh ◽

Shih-Hsu Huang ◽

Chun-Hua Cheng

Keyword(s):

High Level Synthesis ◽

Formal Approach ◽

High Level

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Towards a specification notation for high-level synthesis of mixed-signal and analog systems

Proceedings 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation ◽

10.1109/bmas.2000.888373 ◽

2002 ◽

Author(s):

A. Doboli ◽

R. Vemuri

Keyword(s):

High Level Synthesis ◽

Mixed Signal ◽

Analog Systems ◽

High Level

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A formal approach to the scheduling problem in high level synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.75629 ◽

1991 ◽

Vol 10 (4) ◽

pp. 464-475 ◽

Cited By ~ 271

Author(s):

C.-T. Hwang ◽

J.-H. Lee ◽

Y.-C. Hsu

Keyword(s):

High Level Synthesis ◽

Scheduling Problem ◽

Formal Approach ◽

High Level

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Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e92.a.3169 ◽

2009 ◽

Vol E92-A (12) ◽

pp. 3169-3179 ◽

Cited By ~ 7

Author(s):

Akira OHCHI ◽

Nozomu TOGAWA ◽

Masao YANAGISAWA ◽

Tatsuo OHTSUKI

Keyword(s):

High Level Synthesis ◽

High Level

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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e100.a.1439 ◽

2017 ◽

Vol E100.A (7) ◽

pp. 1439-1451

Author(s):

Koki IGAWA ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

High Level Synthesis ◽

Synthesis Algorithm ◽

Body Biasing ◽

High Level ◽

Delay Variation

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Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e97.a.2498 ◽

2014 ◽

Vol E97.A (12) ◽

pp. 2498-2506

Author(s):

Akihiro SUDA ◽

Hideki TAKASE ◽

Kazuyoshi TAKAGI ◽

Naofumi TAKAGI

Keyword(s):

High Level Synthesis ◽

Loop Parallelization ◽

Polyhedral Optimization ◽

High Level ◽

Nested Loop

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A parallel ant colony optimization to globally optimize area in high-level synthesis. (c2011)

10.26756/th.2011.36 ◽

2011 ◽

Author(s):

David Elias Kozhaya

Keyword(s):

Ant Colony Optimization ◽

Ant Colony ◽

High Level Synthesis ◽

High Level

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