Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only)

Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '13 ◽

10.1145/2435264.2435315 ◽

2013 ◽

Author(s):

Anh-Tuan Hoang ◽

Takeshi Fujino

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