Design Automation and Test Solutions for Monolithic 3D ICs

Monolithic 3D (M3D) is an emerging heterogeneous integration technology that overcomes the limitations of the conventional through-silicon-via (TSV) and provides significant performance uplift and power reduction. However, the ultra-dense 3D interconnects impose significant challenges during physical design on how to best utilize them. Besides, the unique low-temperature fabrication process of M3D requires dedicated design-for-test mechanisms to verify the reliability of the chip. In this article, we provide an in-depth analysis on these design and test challenges in M3D. We also provide a comprehensive survey of the state-of-the-art solutions presented in the literature. This article encompasses all key steps on M3D physical design, including partitioning, placement, clock routing, and thermal analysis and optimization. In addition, we provide an in-depth analysis of various fault mechanisms, including M3D manufacturing defects, delay faults, and MIV (monolithic inter-tier via) faults. Our design-for-test solutions include test pattern generation for pre/post-bond testing, built-in-self-test, and test access architectures targeting M3D.

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Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/3453480 ◽

2021 ◽

Vol 26 (5) ◽

pp. 1-25

Author(s):

Heechun Park ◽

Bon Woong Ku ◽

Kyungwook Chang ◽

Da Eun Shim ◽

Sung Kyu Lim

Keyword(s):

State Of The Art ◽

Physical Design ◽

Design Flow ◽

Design Tools ◽

Mixed Design ◽

Power Performance ◽

3D Design ◽

Qualitative And Quantitative ◽

3D Ics ◽

Power Delay Product

Studies have shown that monolithic 3D ( M3D ) ICs outperform the existing through-silicon-via ( TSV ) -based 3D ICs in terms of power, performance, and area ( PPA ) metrics, primarily due to the orders of magnitude denser vertical interconnections offered by the nano-scale monolithic inter-tier vias. In order to facilitate faster industry adoption of the M3D technologies, physical design tools and methodologies are essential. Recent academic efforts in developing an EDA algorithm for 3D ICs, mainly targeting placement using TSVs, are inadequate to provide commercial-quality GDS layouts. Lately, pseudo-3D approaches have been devised, which utilize commercial 2D IC EDA engines with tricks that help them operate as an efficient 3D IC CAD tool. In this article, we provide thorough discussions and fair comparisons (both qualitative and quantitative) of the state-of-the-art pseudo-3D design flows, with analysis of limitations in each design flow and solutions to improve their PPA metrics. Moreover, we suggest a hybrid pseudo-3D design flow that achieves both benefits. Our enhancements and the inter-mixed design flow, provide up to an additional 26% wirelength, 10% power consumption, and 23% of power-delay-product improvements.

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Design for Test and Diagnosis of Power Switches

Journal of Circuits System and Computers ◽

10.1142/s0218126616400132 ◽

2015 ◽

Vol 25 (03) ◽

pp. 1640013

Author(s):

Miroslav Valka ◽

Alberto Bosio ◽

Luigi Dilillo ◽

Patrick Girard ◽

Arnaud Virazel ◽

...

Keyword(s):

Power Consumption ◽

Industrial Test ◽

Design For Test ◽

Power Gating ◽

Test Quality ◽

Worst Case ◽

Manufacturing Defects ◽

Efficient Test ◽

Power Switches ◽

Static Power

Power gating techniques have been adopted so far to reduce the static power consumption of integrated circuits (ICs). Power gating is usually implemented by means of several power switches (PSs). Manufacturing defects affecting PSs can lead to increase in the actual static power consumption and, in the worst case, they can completely isolate a functional block in the IC. Thus, efficient test and diagnosis solutions are needed. In this paper, we present a novel Design for Test and Diagnosis (DfTD) solution able to increase the test quality and diagnosis accuracy of PSs. The proposed approach has been validated through SPICE simulations on ITC’99 benchmark circuits as well as on industrial test cases.

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RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs

Proceedings of the 56th Annual Design Automation Conference 2019 on - DAC '19 ◽

10.1145/3316781.3323486 ◽

2019 ◽

Cited By ~ 2

Author(s):

Heechun Park ◽

Kyungwook Chang ◽

Bon Woong Ku ◽

Jinwoo Kim ◽

Edward Lee ◽

...

Keyword(s):

Design For Test ◽

3D Ics

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Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application

IET Computers & Digital Techniques ◽

10.1049/iet-cdt.2008.0072 ◽

2009 ◽

Vol 3 (5) ◽

pp. 487 ◽

Cited By ~ 15

Author(s):

X.-T. Tran ◽

Y. Thonnart ◽

J. Durupt ◽

V. Beroulle ◽

C. Robach

Keyword(s):

Test Pattern ◽

Network On Chip ◽

Pattern Generation ◽

Test Pattern Generation ◽

Design For Test ◽

Asynchronous Network ◽

On Chip

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Hybrid Cooperative Energy Detection Techniques in Cognitive Radio Networks

Advances in Wireless Technologies and Telecommunication - Handbook of Research on Software-Defined and Cognitive Radio Technologies for Dynamic Spectrum Management ◽

10.4018/978-1-4666-6571-2.ch001 ◽

2015 ◽

pp. 1-37 ◽

Cited By ~ 1

Author(s):

Raza Umar ◽

Fahham Mohammed ◽

Mohamed Deriche ◽

Asrar U. H. Sheikh

Keyword(s):

Cognitive Radio ◽

A Priori ◽

Energy Detection ◽

Communication Overhead ◽

Test Statistic ◽

Local Data ◽

Secondary Users ◽

Detection Techniques ◽

Depth Analysis ◽

Significant Performance

Cognitive Radio (CR) has emerged as a smart solution to spectrum bottleneck faced by current wireless services under which licensed spectrum is made available to unlicensed Secondary Users (SUs) through robust and efficient Spectrum Sensing (SS). Energy Detection (ED) is the dominantly used SS approach owing to its low computational complexity and ability to identify spectrum holes without requiring a priori knowledge of primary transmission characteristics. In this chapter, the authors present an in-depth analysis of the ED test statistic. Based on the double threshold ED, they analyze the performance of a Hybrid PSO-OR (Particle Swarm Optimization and OR) algorithm for cooperative SS. The sensing decision of “fuzzy” SUs is optimized using PSO and the final collective decision is made based on OR rule. The idea of using two thresholds is introduced to reduce the communication overhead in reporting local data/decision to the fusion center, which also offers reduced energy consumption. The Hybrid PSO-OR algorithm is shown to exhibit significant performance gain over the Hybrid EGC-OR algorithm.

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