Telomere: Real-Time NAND Flash Storage

2022 ◽  
Vol 21 (1) ◽  
pp. 1-24
Author(s):  
Katherine Missimer ◽  
Manos Athanassoulis ◽  
Richard West

Modern solid-state disks achieve high data transfer rates due to their massive internal parallelism. However, out-of-place updates for flash memory incur garbage collection costs when valid data needs to be copied during space reclamation. The root cause of this extra cost is that solid-state disks are not always able to accurately determine data lifetime and group together data that expires before the space needs to be reclaimed. Real-time systems found in autonomous vehicles, industrial control systems, and assembly-line robots store data from hundreds of sensors and often have predictable data lifetimes. These systems require guaranteed high storage bandwidth for read and write operations by mission-critical real-time tasks. In this article, we depart from the traditional block device interface to guarantee the high throughput needed to process large volumes of data. Using data lifetime information from the application layer, our proposed real-time design, called Telomere , is able to intelligently lay out data in NAND flash memory and eliminate valid page copies during garbage collection. Telomere’s real-time admission control is able to guarantee tasks their required read and write operations within their periods. Under randomly generated tasksets containing 500 tasks, Telomere achieves 30% higher throughput with a 5% storage cost compared to pre-existing techniques.

2011 ◽  
Vol 60 (8) ◽  
pp. 1126-1141 ◽  
Author(s):  
Jong-Chan Kim ◽  
Duhee Lee ◽  
Chang-Gun Lee ◽  
Kanghee Kim

Author(s):  
Raja Subramani ◽  
Haritima Swapnil ◽  
Niharika Thakur ◽  
Bharath Radhakrishnan ◽  
Krishnamurthy Puttaiah

Author(s):  
Myungsub Lee

In this paper, we propose a block classification with monitor and restriction (BCMR) method to isolate and reduce the interference of blocks in garbage collection and wear leveling. The proposed method monitors the endurance variation of blocks during garbage collection and detects hot blocks by making a restriction condition based on this information. This method induces block classification by its update frequency for garbage collection and wear leveling, resulting in a prolonged lifespan for NAND flash memory systems. The performance evaluation results show that the BCMR method prolonged the life of NAND flash memory systems by 3.95% and reduced the standard deviation per block by 7.4%, on average.


2014 ◽  
Vol 513-517 ◽  
pp. 2094-2098 ◽  
Author(s):  
Wen Zhe Zhao ◽  
Kai Zhao ◽  
Qiu Bo Chen ◽  
Min Jie Lv ◽  
Zuo Xun Hou

This paper concerns the design of high-speed and low-cost LDPC code bit-flipping decoder. Due to its inferior error correction strength, bit-flipping decoding received very little attention compared with message-passing decoding. Nevertheless, emerging flash-based solid-state data storage systems inherently favor a hybrid bit-flipping/message-passing decoding strategy, due to the significant dynamics and variation of NAND flash memory raw storage reliability. Therefore, for the first time highly efficient silicon implementation of bit-flipping decoder becomes a practically relevant topic. To address the drawbacks caused by the global search operation in conventional bit-flipping decoding, this paper presents a novel bit-flipping decoder design. Decoding simulations and ASIC design show that the proposed design solution can achieve upto 80% higher decoding throughput and meanwhile consume upto 50% less silicon cost, while maintaining almost the same decoding error correction strength.


2014 ◽  
Vol 61 (4) ◽  
pp. 1119-1132 ◽  
Author(s):  
Shuhei Tanakamaru ◽  
Masafumi Doi ◽  
Ken Takeuchi

Author(s):  
Jong-Chan Kim ◽  
Duhee Lee ◽  
Chang-Gun Lee ◽  
Kanghee Kim ◽  
Eun Yong Ha

Sign in / Sign up

Export Citation Format

Share Document