scholarly journals Fault Injection Attack Emulation Framework for Early Evaluation of IC Designs

2022 ◽  
Vol 27 (1) ◽  
pp. 1-25
Author(s):  
Qiang Liu ◽  
Honghui Tang ◽  
Peiran Zhang
Keyword(s):  
Fault Tolerance ◽  
Integrated Circuits ◽  
Fault Injection ◽  
Evaluation Framework ◽  
Design Stage ◽  
Early Evaluation ◽  
Evaluation Approach ◽  
Area Overhead ◽  
Full Scan ◽  
Fault Injection Attack

Fault injection attack (FIA) has become a serious threat to the confidentiality and fault tolerance of integrated circuits (ICs). Circuit designers need an effective method to evaluate the countermeasures of the IC designs against the FIAs at the design stage. To address the need, this article, based on FPGA emulation, proposes an in-circuit early evaluation framework, in which FIAs are emulated with parameterized fault models. To mimic FIAs, an efficient scan approach is proposed to inject faults at any time at any circuit nodes, while both the time and area overhead of fault injection are reduced. After the circuit design under test (CUT) is submitted to the framework, the scan chains insertion, fault generation, and fault injection are executed automatically, and the evaluation result of the CUT is generated, making the evaluation a transparent process to the designers. Based on the framework, the confidentiality and fault-tolerance evaluations are demonstrated with an information-based evaluation approach. Experiment results on a set of ISCAS89 benchmark circuits show that on average, our approach reduces the area overhead by 41.08% compared with the full scan approach and by over 20.00% compared with existing approaches. The confidentiality evaluation experiments on AES-128 and DES-56 and the fault-tolerance evaluation experiments on two CNN circuits, a RISC-V core, a Cordic core, and the float point arithmetic units show the effectiveness of the proposed framework.

Timing Sensitivity Analysis of Logical Nodes in Scan Design Integrated Circuits by Pulsed Diode Laser Stimulation

2008 ◽  
Author(s):  
T. Kiyan ◽  
C. Boit ◽  
C. Brillert
Keyword(s):  
Laser Pulse ◽  
Integrated Circuits ◽  
Continuous Wave ◽  
Fault Injection ◽  
Scan Design ◽  
Flip Flop ◽  
Laser Stimulation ◽  
Scan Chain ◽  
P Type ◽  
Scan Pattern

Abstract In this paper, a methodology based upon laser stimulation and a comparison of continuous wave and pulsed laser operation will be presented that localizes the fault relevant sites in a fully functional scan chain cell. The technique uses a laser incident from the backside to inject soft faults into internal nodes of a master-slave scan flip-flop in consequence of localized photocurrent. Depending on the illuminated type of the transistors (n- or p-type), injection of a logic ‘0’ or ‘1’ into the master or the slave stage of a flip-flop takes place. The laser pulse is externally triggered and can easily be shifted to various time slots in reference to clock and scan pattern. This feature of the laser diode allows triggering the laser pulse on the rising or the falling edge of the clock. Therefore, it is possible to choose the stage of the flip-flop in which the fault injection should occur. It is also demonstrated that the technique is able to identify the most sensitive signal condition for fault injection with a better time resolution than the pulse width of the laser, a significant improvement for failure analysis of integrated circuits.

Physical security of deep learning on edge devices: Comprehensive evaluation of fault injection attack vectors

2021 ◽  
Vol 120 ◽  
pp. 114116
Author(s):  
Xiaolu Hou ◽  
Jakub Breier ◽  
Dirmanto Jap ◽  
Lei Ma ◽  
Shivam Bhasin ◽  
...  
Keyword(s):  
Deep Learning ◽  
Comprehensive Evaluation ◽  
Fault Injection ◽  
Physical Security ◽  
Fault Injection Attack

scholarly journals ARINC653 Channel Robustness Verification Using LeonViP-MC, a LEON4 Multicore Virtual Platform

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1179
Author(s):  
Jonatan Sánchez ◽  
Antonio da Silva ◽  
Pablo Parra ◽  
Óscar R. Polo ◽  
Agustín Martínez Hellín ◽  
...  
Keyword(s):  
Fault Tolerance ◽  
Architectural Design ◽  
Fault Injection ◽  
Control Unit ◽  
Tolerance Mechanisms ◽  
Efficient Data ◽  
Instrument Control ◽  
Virtual Platform ◽  
Hardware Platforms ◽  
The University

Multicore hardware platforms are being incorporated into spacecraft on-board systems to achieve faster and more efficient data processing. However, such systems lead to increased complexity in software development and represent a considerable challenge, especially concerning the runtime verification of fault-tolerance requirements. To address the ever-challenging verification of this kind of requirement, we introduce a LEON4 multicore virtual platform called LeonViP-MC. LeonViP-MC is an evolution of a previous development called Leon2ViP, carried out by the Space Research Group of the University of Alcalá (SRG-UAH), which has been successfully used in the development and testing of the flight software of the instrument control unit (ICU) of the energetic particle detector (EPD) on board the Solar Orbiter. This paper describes the LeonViP-MC architectural design decisions oriented towards fault-injection campaigns to verify software fault-tolerance mechanisms. To validate the simulator, we developed an ARINC653 communications channel that incorporates fault-tolerance mechanisms and is currently being used to develop a hypervisor level for the GR740 platform.

Operating Reliability Assessment of FPGA-Based NPP I&C Systems: Approach, Technique and Implementation

2017 ◽  
Author(s):  
Eugene Babeshko ◽  
Ievgenii Bakhmach ◽  
Vyacheslav Kharchenko ◽  
Eugene Ruchkov ◽  
Oleksandr Siora
Keyword(s):  
Integrated Circuits ◽  
Nuclear Power ◽  
Power Plants ◽  
Failure Modes ◽  
New Technologies ◽  
Systems Approach ◽  
Reliability Assessment ◽  
Design Stage ◽  
Fpga Design ◽  
Operating Reliability

Operating reliability assessment of instrumentation and control systems (I&Cs) is always one of the most important activities, especially for critical domains like nuclear power plants (NPPs). Intensive use of relatively new technologies like field programmable gate arrays (FPGAs) in I&C which appear in upgrades and in newly built NPPs makes task to develop and validate advanced operating reliability assessment methods that consider specific technology features very topical. Increased integration densities make the reliability of integrated circuits the most crucial point in modern NPP I&Cs. Moreover, FPGAs differ in some significant ways from other integrated circuits: they are shipped as blanks and are very dependent on design configured into them. Furthermore, FPGA design could be changed during planned NPP outage for different reasons. Considering all possible failure modes of FPGA-based NPP I&C at design stage is a quite challenging task. Therefore, operating reliability assessment is one of the most preferable ways to perform comprehensive analysis of FPGA-based NPP I&Cs. This paper summarizes our experience on operating reliability analysis of FPGA based NPP I&Cs.

Abstract W P274: Developmental Evaluation Enhances Utility of the Toronto Stroke Networks Virtual Community of Practice

Stroke ◽  
2014 ◽  
Vol 45 (suppl_1) ◽  
Author(s):  
Joanne Fortin ◽  
Krystyna Skryabka ◽  
Gail Avinoam ◽  
Shelley Sharp ◽  
Jacqueline Willems ◽  
...  
Keyword(s):  
Community Of Practice ◽  
Interprofessional Collaboration ◽  
Healthcare Providers ◽  
Virtual Community ◽  
Stroke Care ◽  
Evaluation Framework ◽  
Developmental Evaluation ◽  
Virtual Community Of Practice ◽  
Evaluation Approach ◽  
Value Add

Background: The Toronto Stroke Networks (TSNs) Virtual Community of Practice (VCoP) was developed to connect stroke healthcare providers (HCPs), enhance professional and organizational stroke expertise, foster implementation of best practices, and improve patient outcomes in stroke care. The VCoP is a secure social media platform fostering cross system interprofessional collaboration (IPC). Purpose: To use formative developmental evaluation to inform further improvement of the VCoP’s content and performance and to measure its efficacy as a KT tool to support IPC. Methods: An evaluation framework was developed based on “Promoting and assessing value creation in communities and networks” (Wengar, 2011). Stroke HCPs from 15 organizations in the TSNs were provided VCoP training to build virtual competence and to seek feedback for enhanced utility. The TSNs Education and KT Implementation Plan for 2013-2014 integrated activities that encourage VCoP use. These activities include co-development of educational material across sites, information sharing between meetings, and to support implementation of specific activities. Qualitative (e.g. value stories, narratives) and quantitative indicators (e.g. membership and usage) data are evaluated. Results: The TSNs VCoP currently has: 287 members and 26 groups (open and private groups with 4-19 members). There are 8 interprofessional discussions, with a total of 20 pre-populated and requested forums. Feedback from the membership has prompted investments to improve search features and identification of members within the site for more efficient collaborations. Uploading of Provincial Stroke Rounds, provision of a Research and Knowledge Translation Widget, and securing a space for HCPs to submit recommended presentations were added to increase the value-add of the site as a one-stop shop for Stroke HCPs seeking stroke care information. Qualitative analysis of value stories demonstrating the efficacy of the VCoP for IPC is in progress and will be available at time of publishing. Conclusions: The VCoP is an innovative approach to enhancing the system of stroke care. This formative developmental evaluation approach has enhanced the utility of the VCoP as a source for stroke information and HCP connections.

A Method to Support Fault Tolerance Design in Service Oriented Computing Systems

2012 ◽  
pp. 362-376
Author(s):  
Domenico Cotroneo ◽  
Antonio Pecchia ◽  
Roberto Pietrantuono ◽  
Stefano Russo
Keyword(s):  
Fault Tolerance ◽  
Common Ground ◽  
Fault Injection ◽  
Failure Behavior ◽  
Tolerance Design ◽  
System Failure ◽  
Computing Systems ◽  
Service Oriented Computing ◽  
Service Oriented ◽  
Tailored Design

Service Oriented Computing relies on the integration of heterogeneous software technologies and infrastructures that provide developers with a common ground for composing services and producing applications flexibly. However, this approach eases software development but makes dependability a big challenge. Integrating such diverse software items raise issues that traditional testing is not able to exhaustively cope with. In this context, tolerating faults, rather than attempt to detect them solely by testing, is a more suitable solution. This paper proposes a method to support a tailored design of fault tolerance actions for the system being developed. This paper describes system failure behavior through an extensive fault injection campaign to figure out its criticalities and adopt the most appropriate countermeasures to tolerate operational faults. The proposed method is applied to two distinct SOC-enabling technologies. Results show how the achieved findings allow designers to understand the system failure behavior and plan fault tolerance.

An Integrated Evaluation Approach for E-Learning Systems in Career and Technical Education

2009 ◽  
pp. 396-407 ◽  
Author(s):  
Wenhao David Huang ◽  
Steven R. Aragon
Keyword(s):  
Cognitive Load ◽  
Learning Process ◽  
Integrated Approach ◽  
Learning Systems ◽  
Evaluation Framework ◽  
Evaluation Data ◽  
Career And Technical ◽  
Evaluation Approach ◽  
E Learning ◽  
Future Evaluation

As E-learning is gaining popularity in higher education, its evaluation becomes more critical than ever, to ensure the achievement of intended learning outcome. The effectiveness of E-learning system evaluation under current practices, however, remains questionable. One reason for such uncertainty is the lack of direct measurement while learning occurs since most evaluation data is collected after the learning process. Thus this chapter proposes an integrated evaluation approach for E-learning systems based on Cognitive Load Theory and grounded in the 4C/ID-model. Both direct and indirect measurements will be deployed in the integrated approach in the context of cognitive load. Furthermore all evaluation data can be translated into practical E-learning design solutions by triangulating with the 4C/ID-model. This chapter also suggests that future evaluation framework on E-learning should include factors from attitudinal and social aspects of learning process.

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