scholarly journals Wideband Sparse Signal Acquisition Based on Serial Multi-Coset Sampling

2018 ◽  
Vol 2018 ◽  
pp. 1-7
Author(s):  
Changjian Liu ◽  
Houjun Wang
Keyword(s):  
Sampling Rate ◽  
Binary Sequence ◽  
Sampling Technique ◽  
Signal Acquisition ◽  
Sensing Matrix ◽  
Pattern Design ◽  
Analog To Digital ◽  
Reconstruction Performance ◽  
Sequence Generator ◽  
Sampling Pattern

Traditional parallel multi-coset sampling (MCS), which has several sub-Analog-to-Digital-Converters (sub-ADCs) working parallelly, is an attractive sub-Nyquist sampling technique for wideband sparse signals. However, the mismatch among sub-ADCs in traditional parallel MCS, such as bias, gain, and timing skew mismatch, degrades the signal acquisition performance greatly. In this paper, a serial MCS scheme based on clocking single ADC with nonuniform clock is proposed. The nonuniform sampling clock is generated by a pseudo-random binary sequence generator. An additional Sample/Hold (S/H) is used to improve the analog bandwidth of the serial MCS. Moreover, universal sampling pattern is designed for the proposed serial MCS. The sampling pattern design should not only maximize the Kruskal rank of compressed sensing matrix but also take the ADC’s sub-Nyquist sampling rate into consideration. Numeral experiments are presented demonstrating that the mismatch among sub-ADCs in traditional parallel MCS degrades the reconstruction performance greatly, and the proposed serial MCS can avoid the mismatch tactfully.

scholarly journals Compact lightweight imager of both gamma rays and neutrons based on a pixelated stilbene scintillator coupled to a silicon photomultiplier array

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Jihwan Boo ◽  
Mark D. Hammig ◽  
Manhee Jeong
Keyword(s):  
Gamma Rays ◽  
Gamma Ray ◽  
Sampling Rate ◽  
High Sensitivity ◽  
Pulse Shape Discrimination ◽  
Nuclear Materials ◽  
Silicon Photomultiplier ◽  
Analog To Digital ◽  
Particle Imaging ◽  
Imaging Plane

AbstractDual particle imaging, in which both neutrons and gamma-rays in the environment can be individually characterized, is particularly attractive for monitoring mixed radiation emitters such as special nuclear materials (SNM). Effective SNM localization and detection benefits from high instrument sensitivity so that real-time imaging or imaging with a limited number of acquired events is enabled. For portable applications, one also desires a dual particle imager (DPI) that is readily deployable. We have developed a hand-held type DPI equipped with a pixelated stilbene-silicon photomultiplier (SiPM) array module and low sampling-rate analog-to-digital converters (ADCs) processed via a multiplexed readout. The stilbene-SiPM array (12 × 12 pixels) is capable of effectively performing pulse shape discrimination (PSD) between gamma-ray and neutron events and neutron/gamma-ray source localization on the imaging plane, as demonstrated with 252Cf neutron/gamma and 137Cs gamma-ray sources. The low sampling rate ADCs connected to the stilbene-SiPM array module result in a compact instrument with high sensitivity that provides a gamma-ray image of a 137Cs source, producing 6.4 μR/h at 1 m, in less than 69 s. A neutron image for a 3.5 × 105 n/s 252Cf source can also be obtained in less than 6 min at 1 m from the center of the system. The instrument images successfully with field of view of 50° and provides angular resolution of 6.8°.

An Encoder Used in an Ultra High-Speed Folding and Interpolating ADC

2014 ◽  
Vol 1049-1050 ◽  
pp. 687-690
Author(s):  
Yu Han Gao ◽  
Ru Zhang Li ◽  
Dong Bing Fu ◽  
Yong Lu Wang ◽  
Zheng Ping Zhang
Keyword(s):  
High Speed ◽  
Binary Code ◽  
Sampling Rate ◽  
Gray Code ◽  
Cmos Technology ◽  
Careful Consideration ◽  
Analog To Digital ◽  
Interleaved Adc ◽  
Time Interleaved ◽  
Error Suppression

High speed encoder is the key element of high speed analog-to-digital converter (ADC). Therefor the type of encoder, the type of code, bubble error suppression and bit synchronization must be taken into careful consideration especially for folding and interpolating ADC. To reduce the bubble error which may resulted from the circuit niose, comparator metastability and other interference, the output of quantizer is first encoded with gray code and then converted to binary code. This high speed encoder is verified in the whole time-interleaved ADC with 0.18 Bi-CMOS technology, the whole ADC can achieve a SNR of 45 dB at the sampling rate of 5GHz and input frequency of 495MHz, meanwhile a bit error rate (BER) of less than 10-16 is ensured by this design.

scholarly journals A Statistic-Based Calibration Method for TIADC System

2015 ◽  
Vol 2015 ◽  
pp. 1-9 ◽  
Author(s):  
Kuojun Yang ◽  
Shulin Tian ◽  
Peng Ye ◽  
Peng Zhang ◽  
Yuanjin Zheng
Keyword(s):  
Sampling Rate ◽  
Calibration Method ◽  
Wide Frequency Range ◽  
Accurate Estimation ◽  
Analog To Digital ◽  
Average Value ◽  
Gain Error ◽  
Sampling Points ◽  
Interleaved Adc ◽  
Time Interleaved

Time-interleaved technique is widely used to increase the sampling rate of analog-to-digital converter (ADC). However, the channel mismatches degrade the performance of time-interleaved ADC (TIADC). Therefore, a statistic-based calibration method for TIADC is proposed in this paper. The average value of sampling points is utilized to calculate offset error, and the summation of sampling points is used to calculate gain error. After offset and gain error are obtained, they are calibrated by offset and gain adjustment elements in ADC. Timing skew is calibrated by an iterative method. The product of sampling points of two adjacent subchannels is used as a metric for calibration. The proposed method is employed to calibrate mismatches in a four-channel 5 GS/s TIADC system. Simulation results show that the proposed method can estimate mismatches accurately in a wide frequency range. It is also proved that an accurate estimation can be obtained even if the signal noise ratio (SNR) of input signal is 20 dB. Furthermore, the results obtained from a real four-channel 5 GS/s TIADC system demonstrate the effectiveness of the proposed method. We can see that the spectra spurs due to mismatches have been effectively eliminated after calibration.

Area-Efficient Capacitor-Splitting Switching Scheme with a Nearly Constant Common-Mode Voltage for SAR ADCs

2019 ◽  
Vol 29 (10) ◽  
pp. 2020005
Author(s):  
Hao Wang ◽  
Wenming Xie ◽  
Zhixin Chen
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Switching Scheme ◽  
Common Mode ◽  
Analog To Digital ◽  
Common Mode Voltage ◽  
Switching Method ◽  
Area Efficient

A novel area-efficient switching scheme is proposed for the successive approximation register (SAR) analog-to-digital converters (ADCs). The capacitor-splitting structure, charge-average switching technique, and [Formula: see text] (equal to [Formula: see text]/4) are combined together and optimized to realize the proposed switching scheme. [Formula: see text] is only used in the last two bit cycles, which affects the ADC accuracy little and reduces capacitor area by half. It achieves a 98% less switching energy and an 87.5% less capacitor area compared with the conventional switching method. In addition, the DAC output common-mode voltage is approximately constant. Thus, the proposed switching method is a good tradeoff among power consumption, capacitor area, DAC output common-mode voltage, and ADC accuracy. The proposed SAR ADC is simulated in 0.18[Formula: see text][Formula: see text]m CMOS technology with a supply voltage of 0.6[Formula: see text]V and at a sampling rate of 20[Formula: see text]kS/s. The signal-to-noise-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 58.2 and 73.7[Formula: see text]dB, respectively. The effective number of bits (ENOB) is 9.4. It consumes 42[Formula: see text]nW, resulting in a figure-of-merit (FoM) of 3.11 fJ/conversion-step.

scholarly journals A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1100
Author(s):  
Deeksha Verma ◽  
Khuram Shehzad ◽  
Danial Khan ◽  
Sung Jin Kim ◽  
Young Gun Pu ◽  
...  
Keyword(s):  
Low Power ◽  
Sampling Rate ◽  
Complementary Metal Oxide Semiconductor ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Clock Generation ◽  
Analog Converter ◽  
Asynchronous Sar

A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique is proposed. The proposed switching technique consumes only 63.75 CVREF2 switching energy, which is far less as compared to the conventional switching technique without dividing or adding additional switches. In addition, bootstrap switching is implemented to ensure enhanced linearity. To reduce the power consumption from the comparator, a dynamic latch comparator with a self-comparator clock generation circuit is implemented. The proposed prototype of the SAR ADC is implemented in a 55 nm CMOS (complementary metal-oxide-semiconductor) process. The proposed architecture achieves a figure of merit (FOM) of 17.4 fJ/conversion, signal-to-noise distortion ratio (SNDR) of 60.39 dB, and an effective number of bits (ENOB) of 9.74 bits with a sampling rate of 1 MS/s at measurement levels. The implemented SAR ADC consumes 14.8 µW power at 1 V power supply.

Sign in / Sign up

Export Citation Format

Share Document