scholarly journals An efficient design of 45-nm CMOS low-noise charge sensitive amplifier for wireless receivers

2022 ◽  
Vol 12 (2) ◽  
pp. 1274
Author(s):  
Islam T. Almalkawi ◽  
Ashraf H. Al-Bqerat ◽  
Awni Itradat ◽  
Jamal N. Al-Karaki
Keyword(s):  
Power Consumption ◽  
Signal To Noise Ratio ◽  
Cmos Technology ◽  
Channel Length ◽  
Low Noise ◽  
Efficient Design ◽  
Wireless Devices ◽  
Noise Spectral Density ◽  
Wireless Applications ◽  
Amplifier Design

<p>Amplifiers are widely used in signal receiving circuits, such as antennas, medical imaging, wireless devices and many other applications. However, one of the most challenging problems when building an amplifier circuit is the noise, since it affects the quality of the intended received signal in most wireless applications. Therefore, a preamplifier is usually placed close to the main sensor to reduce the effects of interferences and to amplify the received signal without degrading the signal-to-noise ratio. Although different designs have been optimized and tested in the literature, all of them are using larger than 100 nm technologies which have led to a modest performance in terms of equivalent noise charge (ENC), gain, power consumption, and response time. In contrast, we consider in this paper a new amplifier design technology trend and move towards sub 100 nm to enhance its performance. In this work, we use a pre-well-known design of a preamplifier circuit and rebuild it using 45 nm CMOS technology, which is made for the first time in such circuits. Performance evaluation shows that our proposed scaling technology, compared with other scaling technology, extremely reduces ENC of the circuit by more than 95%. The noise spectral density and time resolution are also reduced by 25% and 95% respectively. In addition, power consumption is decreased due to the reduced channel length by 90%. As a result, all of those enhancements make our proposed circuit more suitable for medical and wireless devices.</p>

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

scholarly journals A 2.4 GHz low noise amplifier design at 130nm CMOS technology using common gate topology for WiFi / WiMAX application

2017 ◽  
Vol 7 (1.3) ◽  
pp. 69
Author(s):  
M. Ramana Reddy ◽  
N.S Murthy Sharma ◽  
P. Chandra Sekhar
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Low Power Consumption ◽  
Common Gate ◽  
Chip Size ◽  
Overall Performance ◽  
Amplifier Design ◽  
Noise Amplifier

The proposed work shows an innovative designing in TSMC 130nm CMOS technology. A 2.4 GHz common gate topology low noise amplifier (LNA) using an active inductor to attain the low power consumption and to get the small chip size in layout design. By using this Common gate topology achieves the noise figure of 4dB, Forward gain (S21) parameter of 14.7dB, and the small chip size of 0.26 mm, while 0.8mW power consuming from a 1.1V in 130nm CMOS gives the better noise figure and improved the overall performance.

scholarly journals CMOS Ultra-Wideband Low Noise Amplifier Design

2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
K. Yousef ◽  
H. Jia ◽  
R. Pokharel ◽  
A. Allam ◽  
M. Ragab ◽  
...  
Keyword(s):  
Impedance Matching ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Output Impedance ◽  
Integrated Inductor ◽  
Technology Process ◽  
Amplifier Design ◽  
Noise Amplifier

This paper presents the design of ultra-wideband low noise amplifier (UWB LNA). The proposed UWB LNA whose bandwidth extends from 2.5 GHz to 16 GHz is designed using a symmetric 3D RF integrated inductor. This UWB LNA has a gain of 11 ± 1.0 dB and a NF less than 3.3 dB. Good input and output impedance matching and good isolation are achieved over the operating frequency band. The proposed UWB LNA is driven from a 1.8 V supply. The UWB LNA is designed and simulated in standard TSMC 0.18 µm CMOS technology process.

A Study on Scalability and Variation of CMOS Low Noise Amplifier in Advance CMOS Technology Processes

2016 ◽  
Vol 833 ◽  
pp. 135-139
Author(s):  
Dayang Nur Salmi Dharmiza Awang Salleh ◽  
Rohana Sapawi
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Rf Circuits ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Technology Scaling ◽  
Wireless Applications ◽  
Noise Amplifier ◽  
Technology Processes

Recent technology requires multistandard Radio Frequency (RF) chips for multipurpose wireless applications. In RF circuits, a low-noise amplifier (LNA) plays the key role in determining the receiver’s performance. With CMOS technology scaling, various designs has been adopted to study circuit’s characteristic and variation. In this paper, we present the results of scalable wideband LNA design based on complementary metal oxide semiconductor (CMOS), with its variance study. The design was fabricated in 180nm, 90nm, 65nm and 40nm CMOS technology.

Design of Low Power Integrated CMOS Potentiometric Biosensor for Direct Electronic Detection of DNA Hybridization

2014 ◽  
Vol 67 (1) ◽  
Author(s):  
Wong How Hwan ◽  
Vinny Lam Siu Fan ◽  
Yusmeeraz Yusof
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Dna Hybridization ◽  
Point Of Care ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Channel Length ◽  
Electrical Signal ◽  
Oxide Semiconductor ◽  
Detection Circuit

The purpose of this research is to design a low power integrated complementary metal oxide semiconductor (CMOS) detection circuit for charge-modulated field-effect transistor (CMFET) and it is used for the detection of deoxyribonucleic acid (DNA) hybridization. With the available CMOS technology, it allows the realization of complete systems which integrate the sensing units and transducing elements in the same device. Point-of-care (POC) testing device is a device that allows anyone to operate anywhere and obtain immediate results. One of the important features of POC device is low power consumption because it is normally battery-operated. The power consumption of the proposed integrated CMOS detection circuit requires only 14.87 mW. The detection circuit will amplify the electrical signal that comes from the CMFET to a specified level in order to improve the recording characteristics of the biosensor. Self-cascode topology was used in the drain follower circuit in order to reduce the channel length modulation effect. The proposed detection circuit was designed with 0.18µm Silterra CMOS fabrication process and simulated under Cadence Simulation Tool. 

scholarly journals Signal Conditioning ASIC for the Detection of Combustible Gases

2021 ◽  
Author(s):  
Shelja Kaushal ◽  
Ashwani K. Rana
Keyword(s):  
Power Consumption ◽  
Operating Temperature ◽  
Cmos Technology ◽  
Low Noise ◽  
Working Environment ◽  
Voltage Controlled Oscillator ◽  
Signal Conditioning ◽  
Control Room ◽  
Zero Crossing ◽  
Gas Concentration

In this paper, the signal conditioning ASIC has been designed for transferring the information regarding gas concentration from the hazardous environment of coal mines to the control room. The ASIC is designed to avoid danger in the hazardous working environment with features like high operating temperature, faster response, high sensitivity, and low power consumption. For the desired application, the different modules for ASIC including Low Noise Amplifier (LNA), Voltage Controlled Oscillator (VCO), and Zero Crossing Detector integrated with a buffer are designed based on 180nm CMOS technology node using SCL pdk files on Cadence Virtuoso tool. The overall power consumption of the designed ASIC is 3.92mW with a gain of ~15 and a frequency range of 10KHz to 200KHz for 0.1% gas concentration for a sensor with the operating temperature of ~150oC. The final output of the ASIC is 0V to 1.8V of the square wave which can be further transmitted to the control room.

scholarly journals A 5-nV/√Hz Chopper Negative-R Stabilization Preamplifier for Audio Applications

Micromachines ◽  
2020 ◽  
Vol 11 (5) ◽  
pp. 478
Author(s):  
Jamel Nebhen ◽  
Khaled Alnowaiser ◽  
Stephane Meillere
Keyword(s):  
Supply Voltage ◽  
Signal To Noise Ratio ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Chopper Stabilization ◽  
Main Amplifier ◽  
Measurement Results ◽  
Low Noise Preamplifier

This paper presents a low-noise and low-power audio preamplifier. The proposed low-noise preamplifier employs a delay-time chopper stabilization (CHS) technique and a negative-R circuit, both in the auxiliary amplifier to cancel the non-idealities of the main amplifier. The proposed technique makes it possible to mitigate the preamplifier 1/f noise and thermal noise and improve its linearity. The low-noise preamplifier is implemented in 65 nm complementary metal-oxide semiconductor (CMOS) technology. The supply voltage is 1.2 V, while the power consumption is 159 µW, and the core area is 192 µm2. The proposed circuit of the preamplifier was fabricated and measured. From the measurement results over a signal bandwidth of 20 kHz, it achieves a signal-to-noise ratio (SNR) of 80 dB, an equivalent-input referred noise of 5 nV/√Hz and a noise efficiency factor (NEF) of 1.9 within the frequency range from 1 Hz to 20 kHz.

A LOW POWER CASCADED FEED-FORWARD DELTA-SIGMA MODULATOR FOR RF WIRELESS APPLICATIONS

2009 ◽  
Vol 18 (02) ◽  
pp. 407-429 ◽  
Author(s):  
SHAILESH B. NERURKAR ◽  
KHALID H. ABED
Keyword(s):  
Power Consumption ◽  
Cmos Technology ◽  
Third Order ◽  
Feed Forward ◽  
Analog To Digital ◽  
Wireless Applications ◽  
Fully Differential ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Rf Wireless

This paper presents a design of a novel cascaded third-order feed-forward delta-sigma analog-to-digital converter (ADC). This ADC is realized using fully differential switched capacitor architecture and produces a 12-bit resolution at a data output rate (DOR) of 2.5 MS/s for RF wireless applications. The delta-sigma modulator consists of a second-order single-bit feed-forward modulator cascaded with a multi-bit first-order modulator. The cascaded feed-forward third-order (2-1) ADC is simulated using Matlab and Simulink. The delta-sigma modulator was designed using Cadence Virtuoso in TSMC 0.18 μm CMOS technology. The power consumption of the designed modulator is 12.74 mW, and the resolution is 11.85 bits for an over-sampling ratio (M = 32). The figure of merit is 1.38 pJ at a sample rate of 80 MS/s. The proposed delta-sigma modulator is compared with other state-of-the-art low-pass delta-sigma modulators in terms of their speed, power, DOR, and the proposed modulator has one of the lowest power consumption.

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