scholarly journals 1.3 kV Vertical GaN-Based Trench MOSFETs on 4-Inch Free Standing GaN Wafer

2022 ◽  
Vol 17 (1) ◽  
Author(s):  
Wei He ◽  
Jian Li ◽  
Zeliang Liao ◽  
Feng Lin ◽  
Junye Wu ◽  
...  
Keyword(s):  
Physical Model ◽  
Computer Aided Design ◽  
Figure Of Merit ◽  
Gate Dielectric ◽  
Comprehensive Analysis ◽  
Experiment Data ◽  
Free Standing ◽  
Simulation Data ◽  
Acid Cleaning ◽  
Aided Design

AbstractIn this work, a vertical gallium nitride (GaN)-based trench MOSFET on 4-inch free-standing GaN substrate is presented with threshold voltage of 3.15 V, specific on-resistance of 1.93 mΩ·cm2, breakdown voltage of 1306 V, and figure of merit of 0.88 GW/cm2. High-quality and stable MOS interface is obtained through two-step process, including simple acid cleaning and a following (NH4)2S passivation. Based on the calibration with experiment, the simulation results of physical model are consistent well with the experiment data in transfer, output, and breakdown characteristic curves, which demonstrate the validity of the simulation data obtained by Silvaco technology computer aided design (Silvaco TCAD). The mechanisms of on-state and breakdown are thoroughly studied using Silvaco TCAD physical model. The device parameters, including n−-GaN drift layer, p-GaN channel layer and gate dielectric layer, are systematically designed for optimization. This comprehensive analysis and optimization on the vertical GaN-based trench MOSFETs provide significant guide for vertical GaN-based high power applications.

scholarly journals A New Split Gate Resurf Stepped Oxide UMOSFET Structure with High Doped Epitaxial Layer for Improving Figure of Merit (FOM)

2020 ◽  
Vol 10 (21) ◽  
pp. 7895
Author(s):  
Runze Chen ◽  
Lixin Wang ◽  
Hongkai Zhang ◽  
Mengyao Cui ◽  
Min Guo
Keyword(s):  
Electric Field ◽  
Epitaxial Layer ◽  
Computer Aided Design ◽  
Figure Of Merit ◽  
Cost Effective ◽  
Oxide Semiconductor ◽  
Fabrication Procedure ◽  
Conventional Structure ◽  
Aided Design ◽  
Reduced Surface

The split gate resurf stepped oxide with highly doped epitaxial layer (HDSGRSO) UMOSFET has been proposed. The epitaxial layer of HDSGRSO u-shape metal oxide semiconductor field effect transistor (UMOSFET) has been divided into three parts: the upper epitaxial layer, the lower epitaxial layer and the middle epitaxial layer with higher doping concentration. The research shows that the reduced SURface field (RESURF) active has been enhanced due to the high doped epitaxial layer, which can modulate the electric field distribution and reduce the internal high electric field. Therefore, the HDGRSO UMOSFET has a higher breakdown voltage (BV), a lower on-state specific resistance (RSP) and a better figure of merit (FOM). According to the results of Technology Computer Aided Design (TCAD) simulations, the FOM (BV2/RSP) of HDSGRSO UMOSFET has been improved by 464%, and FOM (RSP × Qgd) of HDSGRSO UMOSFET has been reduced by 27.9% compared to the conventional structure, respectively, when the BV is 240 V. Furthermore, there is no extra special process required in this advanced fabrication procedure, which is relatively cost-effective and achievable.

scholarly journals Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs

Eng ◽  
2021 ◽  
Vol 2 (4) ◽  
pp. 620-631
Author(s):  
Peng Lu ◽  
Can Yang ◽  
Yifei Li ◽  
Bo Li ◽  
Zhengsheng Han
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Gate Dielectric ◽  
Capture Rate ◽  
Three Dimensional ◽  
Silicon On Insulator ◽  
Threshold Voltage Shift ◽  
Space Applications ◽  
Effect Transistor ◽  
Aided Design

The fin field-effect transistor (FinFET) has been the mainstream technology on the VLSI platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power consumption, superior computational power and high single-event effect (SEE) resistance, shows advantages in integrated circuits for space applications. In this work, a rad-hard design methodology for SOI FinFETs is shown to improve the devices’ tolerance against the Total Ionizing Dose (TID) effect. Since the fin height direction enables a new dimension for design optimization, a 3D Source/Drain (S/D) design combined with a gate dielectric de-footing technique, which has been readily developed for the 14 nm node FinFETs, is proposed as an effective method for SOI FinFETs’ TID hardening. More importantly, the governing mechanism is thoroughly investigated using fully calibrated technology computer-aided design (TCAD) simulations to guide design optimizations. The analysis demonstrates that the 3D rad-hard design can modulate the leakage path in 14 nm node n-type SOI FinFETs, effectively suppress the transistors’ sensitivity to the TID charge and reduce the threshold voltage shift by >2×. Furthermore, the rad-hard design can reduce the electric field in the BOX region and lower its charge capture rate under radiation, further improving the transistor’s robustness.

scholarly journals Design and Investigation of the Junction-Less TFET with Ge/Si0.3Ge0.7/Si Heterojunction and Heterogeneous Gate Dielectric

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 476 ◽  
Author(s):  
Tao Han ◽  
Hongxia Liu ◽  
Shulong Wang ◽  
Shupeng Chen ◽  
Wei Li ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Computer Aided Design ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Source Region ◽  
Ultra Low Power ◽  
Narrow Bandgap ◽  
Order Of Magnitude ◽  
Drain Region ◽  
Aided Design

To improve the on-state current and reduce the miller capacitance of the conventional junction-less tunneling field effect transistor (JLTFET), the junction-less TFET with Ge/Si0.3Ge0.7/Si heterojunction and heterogeneous gate dielectric (H-JLTFET) is investigated by the Technology Computer Aided Design (TCAD) simulation in this paper. The source region uses the narrow bandgap semiconductor material germanium to obtain the higher on-state current; the gate dielectric adjacent to the drain region adopts the low-k dielectric material SiO2, which is considered to reduce the gate-to-drain capacitance effectively. Moreover, the gap region uses the Si0.3Ge0.7 material to decrease the tunneling distance. In addition, the effects of the device sizes, doping concentration and work function on the performance of the H-JLTFET are analyzed systematically. The optimal on-state current and switching ratio of the H-JLTFET can reach 6 µA/µm and 2.6 × 1012, which are one order of magnitude and four orders of magnitude larger than the conventional JLTFET, respectively. Meanwhile, the gate-to-drain capacitance, off-state current and power consumption of the H-JLTFET can be effectively suppressed, so it will have a great potential in future ultra-low power integrated circuit applications.

A Study on the Representation of Examples in Learning Engineering Concepts

2012 ◽  
Author(s):  
Olufunmilola Atilola ◽  
Vimal Viswanathan ◽  
Julie Linsey
Keyword(s):  
Pilot Study ◽  
Physical Model ◽  
Computer Aided Design ◽  
Engineering Students ◽  
Design Thinking ◽  
Solution Space ◽  
New Concepts ◽  
Design Representations ◽  
Aided Design

The use of examples in engineering curricula is a commonly used means to teach engineering students new concepts and ideas; these examples play an important role in teaching engineering students how to become technically competent engineers and designers. Being able to learn from examples and avoid fixation to those examples is an important task in that process. Design fixation is a major constraint in design thinking as it limits the solution space where designers search for their ideas. The experiments described in this paper aims to investigate how students fixate to different types of representations. A pilot study comparing sketched and physical representations of examples shows that students are less likely to fixate to the design specifications of examples provided in the form of physical model, this suggests that they are able to better understand the design limitations of examples presented in the form of a physical model. Based on the preliminary results from this pilot experiment, the framework for a follow-up experiment is developed. This second experiment will explore the trend observed in the pilot study further and will compare how students fixate on and derive information between sketched and computer-aided design representations.

Performance atlases of the workspace for planar 3-DOF parallel manipulators

Robotica ◽  
2000 ◽  
Vol 18 (5) ◽  
pp. 563-568 ◽  
Author(s):  
Xin-Jun Liu ◽  
Jinsong Wang ◽  
Feng Gao
Keyword(s):  
Physical Model ◽  
Optimum Design ◽  
Computer Aided Design ◽  
Solution Space ◽  
Parallel Manipulators ◽  
Performance Characteristics ◽  
Performance Criteria ◽  
Computer Aided ◽  
Aided Design

The design of the robotic mechanisms is most important because they determine the performance characteristics of the robots. This paper concerns the issue of computer-aided design (CAD) for planar 3-DOF parallel robotic mechanisms by means of the physical model of the solution space, which can be used systematically to express the relationships between the performance criteria and all link lengths of one type of the robtic mechanism. The performance atlases of the workspace volume for the manipulators are plotted in the physical model of the solution space. The characteristics of the distribution of the workspace shapes in the physical model of the solution space are presented. The results are useful for the optimum design of the robotic mechanisms. This paper proposes a new way for robotic CAD.

Workspace atlases for the computer aided design of the Delta robot

2003 ◽  
Vol 217 (8) ◽  
pp. 861-869 ◽  
Author(s):  
X-J Liu ◽  
J Wang ◽  
H Zheng
Keyword(s):  
Physical Model ◽  
Optimum Design ◽  
Computer Aided Design ◽  
Solution Space ◽  
Parallel Robots ◽  
New Method ◽  
Performance Criteria ◽  
Computer Aided ◽  
Aided Design

Parallel robots lead to complex kinematics equations, so determination of their workspaces is a challenging issue. The workspace of a robot is not fully characterized by its volume alone; the workspace shape is an important aspect as well. In this paper, the geometric determination of the workspace for Delta robots is presented. The workspace (workspace volume and workspace shape) for the robots is studied systematically in ‘the physical model of the solution space’, which is a useful tool to express relationships between the performance criteria and all link lengths of one type of robotic mechanism. Performance atlases of the workspace volume for the robots are plotted in the physical model of the solution space. The characteristics of the distribution of the workspace shapes in the physical model of the solution space are presented as well. The physical model of the solution space presents a new method for the computer aided design (CAD) of robotic mechanisms. The results are very useful for obtaining the optimum design of robotic mechanisms.

scholarly journals Electrical Characteristics Assessment on Heterojunction Tunnel FET (HTFET) by Optimizing Various High-κ Materials: HfO2/ZrO2

2019 ◽  
Vol 8 (10) ◽  
pp. 393-396 ◽  
Keyword(s):  
Computer Aided Design ◽  
Gate Dielectric ◽  
Dielectric Materials ◽  
Electrical Characteristics ◽  
Back Gate ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Low Power Logic ◽  
Aided Design ◽  
Tcad Simulations

In this paper, DC performance of double gate tunnel field effect transistor with heterojunction has been assessed by various III-V compound semiconductor materials using 2-D Technology Computer Aided Design (TCAD) simulations. Different hetero high-κ dielectric materials like HfO2 , ZrO2 have been incorporated to achieve better electrical characteristics, viz. high ON-state current drivability, improved switching ratio and high tunneling probability. In this work, lower band gap materials have been used as hetero gate dielectric to enhance mobility using band to band tunneling (BTBT), transconductance and steeper subthreshold-slope. The heterojunction TFET (HTFET) then incorporated with various hetero dielectrics (high-κ and low-κ combination), where the ZrO2 – SiO2 combination of dielectric having thickness of 2 nm both in front and back gate, attains maximum value of ION as 1.522 × 10-5 A/µm. The subthreshold swing (ss) has also been recorded best as 23.93 mV/dec in comparison with conventional homo dielectric i.e. SiO2 -SiO2 oxide throughout the 50 nm channel of HTFET as 34.22 mV/dec, can serve as better alternative tunnel FETs in low power logic applications.

scholarly journals Моделирование переходных процессов в полупроводниковых приборах на основе 4H-SiC (учет неполной ионизации легирующих примесей в модуле ATLAS программного пакета SILVACO TCAD)

2019 ◽  
Vol 53 (3) ◽  
pp. 407
Author(s):  
П.А. Иванов ◽  
А.С. Потапов ◽  
Т.П. Самсонова
Keyword(s):  
Physical Model ◽  
Dynamic Characteristics ◽  
Computer Aided Design ◽  
Room Temperature ◽  
Software Module ◽  
Capacitive Element ◽  
Computer Aided ◽  
Simulation Results ◽  
Rc Circuit ◽  
Aided Design

AbstractTransient process in a resistor–capacitor (RC) circuit with a reverse-biased 4 H -SiC p – n diode as the capacitive element is simulated. Simulation is performed with the ATLAS software module from the SILVACO TCAD system for technology computer-aided design (TCAD). An alternative way, to that in ATLAS, to set the parameters of doping impurities partly ionized in 4 H -SiC at room temperature is suggested. (The INCOMPLETE physical model available in the ATLAS module, which describes the incomplete ionization of doping impurities in semiconductors, is unsuitable for simulating the dynamic characteristics of devices.) The simulation results are discussed in relation to previously obtained experimental results.

Technological Process Design for the Flanged Parts Using a LabVIEW Application

2015 ◽  
Vol 760 ◽  
pp. 81-86
Author(s):  
Paulina Spânu ◽  
Bogdan Felician Abaza ◽  
Daniel Cazacu
Keyword(s):  
Process Design ◽  
Metal Forming ◽  
Computer Aided Design ◽  
Price Ratio ◽  
Simulation Data ◽  
Graphical Programming ◽  
Material Utilization ◽  
Aided Design ◽  
High Degree

The metal-forming processes provide a high degree of material utilization, a high working capacity, a high quality of the parts and so on. Taking in account the characteristics of these processes and the current requirements of the market economy, it is necessary to extend the research in the metal-forming field in order to develop new solutions that lead to optimization of the metal-forming technologies and, implicit, to obtain the best quality-price ratio. Also, the software for the simulation, data acquisition, data processing and computer aided design are necessary. This paper presents an application developed ​​using a graphical programming language called LabVIEW, through which, the dimensions of the sheet blank for the flanged parts are calculated based on the specifications of the work drawing, checks the hole flangeability and calculates the force required by the metal-forming processes.

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