DESIGN OF FAULT-TOLERANT CHIP INTERFACES
2020 ◽
Vol 13
(1)
◽
pp. 17-24
Keyword(s):
The article discusses the process of designing the interface of fault-tolerant chips. A redundant internal interface is designed for integrating system components on chips into a single information exchange system. The paper describes the interface for the four-channel construction of the VLSI chip of the BMC SNK. Special attention is paid to the description of interface signals.
2017 ◽
Vol 24
(2)
◽
pp. 204
◽
2001 ◽
Vol 7
(2)
◽
pp. 1
2010 ◽
Vol 16
(4)
◽
pp. 281
◽