A survey and analysis of different lightweight block cipher techniques for resource-constrained devices

Author(s):  
G.C. Madhu ◽  
P. Vijaya Kumar
2021 ◽  
Vol 11 (1) ◽  
pp. 391-398
Author(s):  
M. Sruthi ◽  
Rajkumar Rajasekaran

Abstract The information transmitted in IoT is susceptible to affect the user’s privacy, and hence the information ought to be transmitted securely. The conventional method to assure integrity, confidentiality, and non-repudiation is to first sign the message and then encrypt it. Signcryption is a technique where the signature and the encryption are performed in a single round. The current Signcryption system uses traditional cryptographic approaches that are overloaded for IoT, as it consists of resource-constrained devices and uses the weak session key to encrypt the data. We propose a hybrid Signcryption scheme that employs PRESENT, a lightweight block cipher algorithm to encrypt the data, and the session key is encrypted by ECC. The time taken to signcrypt the proposed Signcryption is better when compared to current Signcryption techniques, as it deploys lightweight cryptography techniques that are devoted to resource-constrained devices.


Security in resource-constrained devices has drawn the great attentions to researchers in recent years. To make secure transmission of critical information in such devices, lightweight cryptography algorithms come in light to large extend. KLEIN has been popular lightweight block cipher used to overcome such issues. In this paper, different architectures of KLEIN block cipher are presented. One of designs enhances the efficiency with regard to the throughput at the expense of a larger area. In order to make such designs, the pipelined registers are placed on different positions in datapath algorithm. The proposed design transforms the data input to protected output with the speed of 2414.13 Mbps for xc5vlx50t-3ff1136 device. In addition, the second design implementation completes either one or more than one round in only one clock and gives energy-efficient and high throughput implementations. Due to this, a trade-off between area and speed can be analyzed for high-speed applications. Moreover, this proposed design shows that with increasing the area of cipher implementation results in more transformation of plaintext into ciphertext. All results are verified and simulated for various families of Xilinx ISE design suite.


Informatica ◽  
2017 ◽  
Vol 28 (1) ◽  
pp. 193-214 ◽  
Author(s):  
Tung-Tso Tsai ◽  
Sen-Shan Huang ◽  
Yuh-Min Tseng

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