scholarly journals Experimental realization of an optical digital comparator using silicon microring resonators

Nanophotonics ◽  
2018 ◽  
Vol 7 (3) ◽  
pp. 669-675 ◽  
Author(s):  
Yonghui Tian ◽  
Huifu Xiao ◽  
Xiaosuo Wu ◽  
Zilong Liu ◽  
Yinghao Meng ◽  
...  

AbstractWe propose and experimentally demonstrate a silicon photonic circuit that can perform the comparison operation of two-bit digital signals based on microring resonators (MRRs). Two binary electrical signals regarded as two operands of desired comparison digital signals are applied to three MRRs to modulate their resonances through the microheaters fabricated on the top of MRRs, respectively (here, one binary electrical signal is applied to two MRRs by a 1×2 electrical power splitter, which means that the two MRRs are modulated by the same binary electrical signal). The comparison results of two binary electrical signals can be obtained at two output ports in the form of light. The proposed device is fabricated on a silicon-on-insulator substrate using the complementary metal-oxide-semiconductor fabrication process, and the dynamic characterization of the device with the operation speed of 10 kbps is demonstrated successfully.

Nanophotonics ◽  
2017 ◽  
Vol 6 (6) ◽  
pp. 1343-1352 ◽  
Author(s):  
Chuantong Cheng ◽  
Beiju Huang ◽  
Xurui Mao ◽  
Zanyun Zhang ◽  
Zan Zhang ◽  
...  

AbstractOptical receivers with potentially high operation bandwidth and low cost have received considerable interest due to rapidly growing data traffic and potential Tb/s optical interconnect requirements. Experimental realization of 65 GHz optical signal detection and 262 GHz intrinsic operation speed reveals the significance role of graphene photodetectors (PDs) in optical interconnect domains. In this work, a novel complementary metal oxide semiconductor post-backend process has been developed for integrating graphene PDs onto silicon integrated circuit chips. A prototype monolithic optoelectronic integrated optical receiver has been successfully demonstrated for the first time. Moreover, this is a firstly reported broadband optical receiver benefiting from natural broadband light absorption features of graphene material. This work is a perfect exhibition of the concept of monolithic optoelectronic integration and will pave way to monolithically integrated graphene optoelectronic devices with silicon ICs for three-dimensional optoelectronic integrated circuit chips.


Nanophotonics ◽  
2018 ◽  
Vol 7 (4) ◽  
pp. 727-733 ◽  
Author(s):  
Huifu Xiao ◽  
Dezhao Li ◽  
Zilong Liu ◽  
Xu Han ◽  
Wenping Chen ◽  
...  

AbstractIn this paper, we propose and experimentally demonstrate an integrated optical device that can implement the logical function of priority encoding from a 4-bit electrical signal to a 2-bit optical signal. For the proof of concept, the thermo-optic modulation scheme is adopted to tune each micro-ring resonator (MRR). A monochromatic light with the working wavelength is coupled into the input port of the device through a lensed fiber, and the four input electrical logic signals regarded as pending encode signals are applied to the micro-heaters above four MRRs to control the working states of the optical switches. The encoding results are directed to the output ports in the form of light. At last, the logical function of priority encoding with an operation speed of 10 Kbps is demonstrated successfully.


Nanophotonics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 1939-1948 ◽  
Author(s):  
Zilong Liu ◽  
Xiaosuo Wu ◽  
Huifu Xiao ◽  
Xu Han ◽  
Wenping Chen ◽  
...  

AbstractThe optical parity checker plays an important role in error detection and correction for high-speed, large-capacity, complex digital optical communication networks, which can be employed to detect and correct the error bits by using a specific coding theory such as introducing error-detecting and correcting codes in communication channels. In this paper, we report an integrated silicon photonic circuit that is capable of implementing the parity checking for binary string with an arbitrary number of bits. The proposed parity checker consisting of parallel cascaded N micro-ring resonators (MRRs) is based on directed logic scheme, which means that the operands applied to MRRs to control the switching states of the MRRs are electrical signals, the operation signals are optical signals, and the final operation results are obtained at the output ports in the form of light. A 3-bit parity checker with an operation speed of 10 kbps, fabricated on a silicon-on-insulator (SOI) platform using a standard commercial complementary metal-oxide-semiconductor (CMOS) process, was experimentally and successfully demonstrated.


2011 ◽  
Vol 222 ◽  
pp. 3-7 ◽  
Author(s):  
Hiroshi Inokawa ◽  
Wei Du ◽  
Mitsuru Kawai ◽  
Hiroaki Satoh ◽  
Atsushi Ono ◽  
...  

A unique single-photon detector is reported, which utilizes scaled-down silicon-on- insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) with single-electron sensitivity, and features low-voltage operation without carrier multiplication and low dark counts. Primary single-photon detection characteristics are presented, and then several issues related to operation speed and quantum efficiency are to be addressed.


2018 ◽  
Vol 7 (2.7) ◽  
pp. 647
Author(s):  
J Lakshmi Prasanna ◽  
V Sahiti ◽  
E Raghuveera ◽  
M Ravi Kumar

A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs. 


2014 ◽  
Vol 116 (7) ◽  
pp. 074513 ◽  
Author(s):  
V. Mikhelashvili ◽  
D. Cristea ◽  
B. Meyler ◽  
S. Yofis ◽  
Y. Shneider ◽  
...  

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