scholarly journals On-chip optical parity checker using silicon photonic integrated circuits

Nanophotonics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 1939-1948 ◽  
Author(s):  
Zilong Liu ◽  
Xiaosuo Wu ◽  
Huifu Xiao ◽  
Xu Han ◽  
Wenping Chen ◽  
...  
Keyword(s):  
Error Detection ◽  
High Speed ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Ring Resonators ◽  
Cmos Process ◽  
Operation Speed ◽  
Parity Checker ◽  
Silicon Photonic ◽  
Error Detection And Correction

AbstractThe optical parity checker plays an important role in error detection and correction for high-speed, large-capacity, complex digital optical communication networks, which can be employed to detect and correct the error bits by using a specific coding theory such as introducing error-detecting and correcting codes in communication channels. In this paper, we report an integrated silicon photonic circuit that is capable of implementing the parity checking for binary string with an arbitrary number of bits. The proposed parity checker consisting of parallel cascaded N micro-ring resonators (MRRs) is based on directed logic scheme, which means that the operands applied to MRRs to control the switching states of the MRRs are electrical signals, the operation signals are optical signals, and the final operation results are obtained at the output ports in the form of light. A 3-bit parity checker with an operation speed of 10 kbps, fabricated on a silicon-on-insulator (SOI) platform using a standard commercial complementary metal-oxide-semiconductor (CMOS) process, was experimentally and successfully demonstrated.

scholarly journals Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 369 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Nikos Mastorakis
Keyword(s):  
High Speed ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Performance Comparison ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Least Significant Bit ◽  
Design Metrics ◽  
Ripple Carry Adder ◽  
Speed Performance

Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing binary-to-excess-1 code (BEC) converters. In the literature, the designs of many CLAs and CSLAs were described separately. It would be useful to have a direct comparison of their performances based on the design metrics. Hence, we implemented homogeneous and hybrid CLAs, and CSLAs with and without the BEC converters by considering 32-bit accurate and approximate additions to facilitate a comparison. For the gate-level implementations, we considered a 32/28 nm complementary metal-oxide-semiconductor (CMOS) process targeting a typical-case process–voltage–temperature (PVT) specification. The results show that the hybrid CLA/RCA architecture is preferable among the CLA and CSLA architectures from the speed and power perspectives to perform accurate and approximate additions.

Multiple System Configurations in a 32-bit Extreme Environment

2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000301-000306 ◽  
Author(s):  
Michael C. Brown
Keyword(s):  
Error Detection ◽  
Extreme Environments ◽  
Extreme Environment ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
System A ◽  
External Sources ◽  
System Configurations ◽  
Simple Systems ◽  
Computational Systems

Full computational systems are needed at extreme environments (to 300°C) to increase functionality and reduce cost in the ever advancing oil/gas, geothermal, aeronautic, and automotive industries. Commercially available electronic components are not available to build a reliable system. A single microcontroller device can be used in systems of varying complexity, from small, mid, large, and multiprocessor scale. The 32-bit microcontroller will use a low power silicon-on-insulator CMOS process to increase long term reliability. Communication ports are provided to allow for simple systems with a single processor to complex multiprocessor systems with multiple controlled devices and external memory. As no adequate non-volatile solution is available for extreme conditions, multiple boot options are available to load instructions from external sources. Fault tolerance should be provided by system error detection. Battery backup must be provided for program and data retention. The resulting microcontroller will allow a wide variety of extreme environment systems, from simple to complex.

scholarly journals 100 Gb/s Silicon Photonic WDM Transmitter with Misalignment-Tolerant Surface-Normal Optical Interfaces

Micromachines ◽  
2019 ◽  
Vol 10 (5) ◽  
pp. 336 ◽  
Author(s):  
Beiju Huang ◽  
Zanyun Zhang ◽  
Zan Zhang ◽  
Chuantong Cheng ◽  
Huang Zhang ◽  
...  
Keyword(s):  
Wavelength Division Multiplex ◽  
Complementary Metal Oxide Semiconductor ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Optical Modulator ◽  
Grating Coupler ◽  
Coupling Loss ◽  
Wavelength Division ◽  
Silicon Photonic ◽  
Fiber Misalignment

A 4 × 25 Gb/s ultrawide misalignment tolerance wavelength-division-multiplex (WDM) transmitter based on novel bidirectional vertical grating coupler has been demonstrated on complementary metal-oxide-semiconductor (CMOS)-compatible silicon-on-insulator (SOI) platform. Simulations indicate the bidirectional grating coupler (BGC) is widely misalignment tolerant, with an excess coupling loss of only 0.55 dB within ±3 μm fiber misalignment range. Measurement shows the excess coupling loss of the BGC is only 0.7 dB within a ±2 μm fiber misalignment range. The bidirectional grating structure not only functions as an optical coupler, but also acts as a beam splitter. By using the bidirectional grating coupler, the silicon optical modulator shows low insertion loss and large misalignment tolerance. The eye diagrams of the modulator at 25 Gb/s don’t show any obvious deterioration within the waveguide-direction fiber misalignment ranger of ±2 μm, and still open clearly when the misalignment offset is as large as ±4 μm.

scholarly journals A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 305 ◽  
Author(s):  
Dong Wang ◽  
Xiaoge Zhu ◽  
Xuan Guo ◽  
Jian Luan ◽  
Lei Zhou ◽  
...  
Keyword(s):  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Power Measurement ◽  
Cmos Process ◽  
Analog To Digital ◽  
Full Speed ◽  
Time Interleaved

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/−0.85 LSB and +0.71/−0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 μm × 550 μm, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step.

scholarly journals Experimental realization of an optical digital comparator using silicon microring resonators

Nanophotonics ◽  
2018 ◽  
Vol 7 (3) ◽  
pp. 669-675 ◽  
Author(s):  
Yonghui Tian ◽  
Huifu Xiao ◽  
Xiaosuo Wu ◽  
Zilong Liu ◽  
Yinghao Meng ◽  
...  
Keyword(s):  
Electrical Signal ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Microring Resonators ◽  
Digital Signals ◽  
Experimental Realization ◽  
Electrical Signals ◽  
Operation Speed ◽  
Digital Comparator ◽  
Comparison Results

AbstractWe propose and experimentally demonstrate a silicon photonic circuit that can perform the comparison operation of two-bit digital signals based on microring resonators (MRRs). Two binary electrical signals regarded as two operands of desired comparison digital signals are applied to three MRRs to modulate their resonances through the microheaters fabricated on the top of MRRs, respectively (here, one binary electrical signal is applied to two MRRs by a 1×2 electrical power splitter, which means that the two MRRs are modulated by the same binary electrical signal). The comparison results of two binary electrical signals can be obtained at two output ports in the form of light. The proposed device is fabricated on a silicon-on-insulator substrate using the complementary metal-oxide-semiconductor fabrication process, and the dynamic characterization of the device with the operation speed of 10 kbps is demonstrated successfully.

Design of High-Speed Decoder for New High-Speed Bus

2010 ◽  
Vol 20-23 ◽  
pp. 958-962
Author(s):  
Wei Gong Zhang ◽  
Bo Yang ◽  
Rui Ding ◽  
Yong Qin Hu
Keyword(s):  
Error Correction ◽  
Intelligent Control ◽  
Error Detection ◽  
High Speed ◽  
Critical Path ◽  
Speed Error ◽  
Error Detection And Correction ◽  
Traditional Algorithm ◽  
New Type ◽  
Correction System

This paper presents a new type of high-speed error correction for the requirements of new high-Speed Bus. Use RS (255, 239). Not only optimization traditional algorithm, but also design bidirectional synchronous calculated adjoint form module, Fast B-M algorithm module. and full parallel Chien Search module. These design used in new high-Speed Bus, Larger than usual decoder designed to significantly shorten the critical path decoding, and achieve continuous decoding. In addition, this error correction system separated error detection and correction module modules, And after error detection module add intelligent control, which reduced the complexity and power consumption of equipment. The error correction system design for the requirements of the new bus which speed is above 400m / s.

Condensation Mechanism for the Formation of Relaxed SiGe Layer Grown-on-Insulator

2008 ◽  
Vol 1068 ◽  
Author(s):  
Hun-Joo Lee ◽  
Gon-Sub Lee ◽  
Young-Soo Han ◽  
Seuck-Hoon Hong ◽  
Tae-Hun Shim ◽  
...  
Keyword(s):  
Surface Property ◽  
High Speed ◽  
Field Effect Transistors ◽  
Sige Layer ◽  
Surface Oxide ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Insulator Layer ◽  
Quality Properties ◽  
Condensation Method

ABSTRACTThe condensation method to grow a strained SiGe layer-on-insulator (ε-SGOI) has attracted interests for the application of high speed complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) because of high quality properties and effective process cost. Although many reports presented its superiority in a device performance to bonding and dislocation sink technologies, the mechanism by which the condensation method produces ε-SGOI has also not been clearly explained and the surface properties have not been evaluated. Thus, we investigated condensation mechanism in detail by characterizing a surface property and Ge profile in SiGe layer. For the experiment, first, a SiGe layer on silicon-on-insulator layer was epitaxally grown at 550 °C, and three different oxidation thicknesses were grown at 950 °C, i.e., 40, 60, 90 nm. From our investigation results, we found that there are three steps in producing ε-SGOI. For the first step, by the 40-nm-thick oxidation, a diffusion of Ge atoms in SiGe layer into Si layer-on-insulator was generated and Ge atoms were segregated into only surface oxide. It was observed that Ge profile of SiGe layer was shown a less graded profile. And, in the second step with 60-nm-thick oxidation, Ge atoms in SiGe layer into Si layer-on-insulator was diffused further than a first step did and Ge atoms were segregated into surface oxide. It was observed that Si layer was shown a fully graded profile. Lastly, in the third step with 90-nm-thick oxidation, the diffusion of Ge atoms in SiGe layer into Si layer-on-insulator was finished completely and Ge atoms were segregated into both surface and buried oxides. It was confirm that Ge profile of SiGe layer was shown a Gaussian profile rather than a graded profile, and dislocation sink occurred. Therefore, our talk will focus on the explanation for the mechanism by which condensation method produces ε-SGOI via characterizing a surface property, SiGe thickness, a remained Si thickness on insulator, and Ge concentration in SiGe layer.

Design of a power-efficient Kogge–Stone adder by exploring new OR gate in 45nm CMOS process

Circuit World ◽  
2020 ◽  
Vol 46 (4) ◽  
pp. 257-269
Author(s):  
Vimukth John ◽  
Shylu Sam ◽  
S. Radha ◽  
P. Sam Paul ◽  
Joel Samuel
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Arithmetic Function ◽  
Logic Circuit ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Content Type ◽  
Simulation Results ◽  
Circuit Power ◽  
Or Gate

Purpose The purpose of this work is to reduce the power consumption of KSA and to improve the PDP for data path applications. In digital Very Large – Scale Integration systems, the addition of two numbers is one of the essential functions. This arithmetic function is used in the modern digital signal processors and microprocessors. The operating speed of these processors depends on the computation of the arithmetic function. The speed computation block for most of the datapath elements was adders. In this paper, the Kogge–Stone adder (KSA) is designed using XOR, AND and proposed OR gates. The proposed OR gate has less power consumption due to the less number of transistors. In arithmetic logic circuit power, delay and power delay products (PDP) are considered as the important parameters. The delays reported for the proposed OR gate are less when compared with the conventional Complementary Metal Oxide Semiconductor (CMOS) OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. To analyze the performance of KSA, extensive Cadence Virtuoso simulations are used. From the simulation results based on 45 nm CMOS process, it was observed that the proposed design has obtained 688.3 nW of power consumption, 0.81 ns of delay and 0.55 fJ of PDP at 1.1 V. Design/methodology/approach In this paper, a new circuit for OR gate is proposed. The KSA is designed using XOR, AND and proposed OR gates. Findings The proposed OR gate has less power consumption due to the less number of transistors. The delays reported for the proposed OR gate are less when compared with the conventional CMOS OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. Originality/value In arithmetic logic circuit power, delay and PDP are considered as the important parameters. In this paper, a new circuit for OR gate is proposed. The power consumption of the designed KSA using the proposed OR gate is very less when compared with the conventional KSA. Simulation results show that the performance of the proposed KSA are improved and suitable for high speed applications.

scholarly journals SEC-TAED based Error Detection and Correction Technique for Data Transmission Systems

2018 ◽  
Vol 10 (2) ◽  
pp. 696
Author(s):  
Mr. G. Manikandan ◽  
Dr. M. Anand
Keyword(s):  
Error Detection ◽  
Gaussian Noise ◽  
Data Transmission ◽  
High Speed ◽  
Additive White Gaussian Noise ◽  
Hamming Code ◽  
Correction Technique ◽  
Error Detection And Correction ◽  
Placement Algorithm ◽  
Original Information

<p>In the OFDM communication system channel encoder and decoder is the part of the architecture. OFDM channel is mostly affected by Additive White Gaussian Noise (AWGN) in which bit flipping of original information leads to fault transmission in the channel. To overcome this problem by using hamming code for error detection and correction. Hamming codes are more attractive and it easy to process the encoding and decoding with low latency. In general the hamming is perfectly detected and corrects the single bit error. In this paper, design of single Error Correction-Triple Adjacent Error Detection (SEC-TAED) codes with bit placement algorithm is presented with less number of parity bits. In the conventional Double Adjacent Error Detection (DAED) and Hamming (13, 8) SEC-TAED are process the codes and detects the error, but it require more parity bits for performing the operation. The higher number of parity bits causes processing delay. To avoid this problem by proposed the Hamming (12, 8) SEC-TAED code, it require only four parity bits to perform the detection process. Bit-reordered format used in the method increases the probability detection of triple adjacent error. It is more suitable for efficient and high speed communication.</p>

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