Folded down-conversion mixer for a 60 GHz receiver architecture in 65-nm CMOS technology

2014 ◽  
Vol 15 (12) ◽  
pp. 1190-1199 ◽  
Author(s):  
Najam Muhammad Amin ◽  
Zhi-gong Wang ◽  
Zhi-qun Li
Keyword(s):  
Cmos Technology ◽  
60 Ghz ◽  
Receiver Architecture ◽  
Down Conversion

60 GHz-Band Low-Noise Amplifier

2017 ◽  
Vol 26 (05) ◽  
pp. 1750075 ◽  
Author(s):  
Najam Muhammad Amin ◽  
Lianfeng Shen ◽  
Zhi-Gong Wang ◽  
Muhammad Ovais Akhter ◽  
Muhammad Tariq Afridi
Keyword(s):  
Transmission Line ◽  
Quality Factor ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Constant Current ◽  
60 Ghz ◽  
Frequency Range ◽  
Constant Current Density ◽  
Chip Area

This paper presents the design of a 60[Formula: see text]GHz-band LNA intended for the 63.72–65.88[Formula: see text]GHz frequency range (channel-4 of the 60[Formula: see text]GHz band). The LNA is designed in a 65-nm CMOS technology and the design methodology is based on a constant-current-density biasing scheme. Prior to designing the LNA, a detailed investigation into the transistor and passives performances at millimeter-wave (MMW) frequencies is carried out. It is shown that biasing the transistors for an optimum noise figure performance does not degrade their power gain significantly. Furthermore, three potential inductive transmission line candidates, based on coplanar waveguide (CPW) and microstrip line (MSL) structures, have been considered to realize the MMW interconnects. Electromagnetic (EM) simulations have been performed to design and compare the performances of these inductive lines. It is shown that the inductive quality factor of a CPW-based inductive transmission line ([Formula: see text] is more than 3.4 times higher than its MSL counterpart @ 65[Formula: see text]GHz. A CPW structure, with an optimized ground-equalizing metal strip density to achieve the highest inductive quality factor, is therefore a preferred choice for the design of MMW interconnects, compared to an MSL. The LNA achieves a measured forward gain of [Formula: see text][Formula: see text]dB with good input and output impedance matching of better than [Formula: see text][Formula: see text]dB in the desired frequency range. Covering a chip area of 1256[Formula: see text][Formula: see text]m[Formula: see text]m including the pads, the LNA dissipates a power of only 16.2[Formula: see text]mW.

A 60 GHz reconfigurable active phase shifter based on a vector modulator in 65 nm CMOS technology

2016 ◽  
Vol 8 (3) ◽  
pp. 399-404 ◽  
Author(s):  
Boris Moret ◽  
Nathalie Deltimple ◽  
Eric Kerhervé ◽  
Baudouin Martineau ◽  
Didier Belot
Keyword(s):  
Phase Shift ◽  
Phase Shifter ◽  
Complementary Metal Oxide Semiconductor ◽  
Active Phase ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
60 Ghz ◽  
Semiconductor Technology ◽  
Vector Modulator ◽  
Active Phase Shifter

This paper presents a 60 GHz reconfigurable active phase shifter based on a vector modulator implemented in 65 nm complementary metal–oxide–semiconductor technology. This circuit is based on the recombination of two differential paths in quadrature. The proposed vector modulator allows us to generate a phase shift between 0° and 360°. The voltage gain varies between −13 and −9 dB in function of the phase shift generated with a static consumption between 26 and 63 mW depending on its configuration.

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

Sign in / Sign up

Export Citation Format

Share Document