NAND And NOR Logic-In-Memory Comprising Silicon Nanowire Feedback Field-Effect Transistors

Author(s):  
Yejin Yang ◽  
Juhee Jeon ◽  
Jaemin Son ◽  
Kyoungah Cho ◽  
Sangsig Kim

Abstract The processing of large amounts of data requires a high energy efficiency and fast processing time for high-performance computing systems. However, conventional von Neumann computing systems have performance limitations because of bottlenecks in data movement between separated processing and memory hierarchy, which causes latency and high power consumption. To overcome this hindrance, logic-in-memory (LIM) has been proposed that performs both data processing and memory operations. Here, we present a NAND and NOR LIM composed of silicon nanowidre feedback field-effect transistors, whose configuration resembles that of CMOS logic gate circuits. The LIM can perform memory operations to retain its output logic under zero-bias conditions as well as logic operations with a high processing speed of nanoseconds. The newly proposed dynamic voltage-transfer characteristics verify the operating principle of the LIM. This study demonstrates that the NAND and NOR LIM has promising potential to resolve power and processing speed issues.

2018 ◽  
Vol 112 (21) ◽  
pp. 213501 ◽  
Author(s):  
Chao Wang ◽  
You Meng ◽  
Zidong Guo ◽  
Byoungchul Shin ◽  
Guoxia Liu ◽  
...  

2012 ◽  
Vol 23 (39) ◽  
pp. 395202 ◽  
Author(s):  
O Shirak ◽  
O Shtempluck ◽  
V Kotchtakov ◽  
G Bahir ◽  
Y E Yaish

Nano Research ◽  
2011 ◽  
Vol 4 (10) ◽  
pp. 1005-1012 ◽  
Author(s):  
Ruo-Gu Huang ◽  
Douglas Tham ◽  
Dunwei Wang ◽  
James R. Heath

2012 ◽  
Vol 11 (04) ◽  
pp. 1240011
Author(s):  
G. ROSAZ ◽  
B. SALEM ◽  
N. PAUC ◽  
P. GENTILE ◽  
A. POTIÉ ◽  
...  

Silicon nanowires (Si NWs) are promising candidates for field-effect transistor (FET) conduction channel. Planar configuration using a back gate is an easy way to study these devices. We demonstrate the possibility to build high performance FET using a simple silicidation process leading to high effective holes' mobility between 130 cm2⋅V-1⋅s-1 and 200 cm2⋅V-1⋅s-1 and good ION/IOFF ratio up to 105. Moreover we investigated the possibility to passivate the NWs using either a high-k dielectric layer or a thermal oxide shell around the NWs. This leads to a reduction of the hysteretic behavior during the gate voltage sweep from 30 V to 1 V depending on the material and the gate configuration.


Nano Letters ◽  
2003 ◽  
Vol 3 (2) ◽  
pp. 149-152 ◽  
Author(s):  
Yi Cui ◽  
Zhaohui Zhong ◽  
Deli Wang ◽  
Wayne U. Wang ◽  
Charles M. Lieber

2009 ◽  
Vol 20 (41) ◽  
pp. 415202 ◽  
Author(s):  
Qiliang Li ◽  
Xiaoxiao Zhu ◽  
Yang Yang ◽  
Dimitris E Ioannou ◽  
Hao D Xiong ◽  
...  

Nanophotonics ◽  
2020 ◽  
Vol 9 (16) ◽  
pp. 4719-4728
Author(s):  
Tao Deng ◽  
Shasha Li ◽  
Yuning Li ◽  
Yang Zhang ◽  
Jingye Sun ◽  
...  

AbstractThe molybdenum disulfide (MoS2)-based photodetectors are facing two challenges: the insensitivity to polarized light and the low photoresponsivity. Herein, three-dimensional (3D) field-effect transistors (FETs) based on monolayer MoS2 were fabricated by applying a self–rolled-up technique. The unique microtubular structure makes 3D MoS2 FETs become polarization sensitive. Moreover, the microtubular structure not only offers a natural resonant microcavity to enhance the optical field inside but also increases the light-MoS2 interaction area, resulting in a higher photoresponsivity. Photoresponsivities as high as 23.8 and 2.9 A/W at 395 and 660 nm, respectively, and a comparable polarization ratio of 1.64 were obtained. The fabrication technique of the 3D MoS2 FET could be transferred to other two-dimensional materials, which is very promising for high-performance polarization-sensitive optical and optoelectronic applications.


2021 ◽  
Vol 13 (1) ◽  
Author(s):  
Muhammad Naqi ◽  
Kyung Hwan Choi ◽  
Hocheon Yoo ◽  
Sudong Chae ◽  
Bum Jun Kim ◽  
...  

AbstractLow-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these semiconductors need to feature large-area fabrication, solution processability, high electrical performance, and wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type semiconductors have been achieved, the development of high-performance p-type semiconductors at low temperature is still limited. Here, we report a unique low-temperature-processed method to synthesize tellurium nanowire networks (Te-nanonets) over a scalable area for the fabrication of high-performance large-area p-type field-effect transistors (FETs) with uniform and stable electrical and optical properties. Maximum mobility of 4.7 cm2/Vs, an on/off current ratio of 1 × 104, and a maximum transconductance of 2.18 µS are achieved. To further demonstrate the applicability of the proposed semiconductor, the electrical performance of a Te-nanonet-based transistor array of 42 devices is also measured, revealing stable and uniform results. Finally, to broaden the applicability of p-type Te-nanonet-based FETs, optical measurements are demonstrated over a wide spectral range, revealing an exceptionally uniform optical performance.


2007 ◽  
Vol 90 (14) ◽  
pp. 142110 ◽  
Author(s):  
M. T. Björk ◽  
O. Hayden ◽  
H. Schmid ◽  
H. Riel ◽  
W. Riess

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