scholarly journals Design of a Fully Integrated VHF CP-PLL Frequency Synthesizer with an All-Digital Defect-Oriented Built-In Self-Test.

2022 ◽  
Author(s):  
Benjamin Kommey ◽  
Ernest Addo ◽  
Jepthah Yankey ◽  
Andrew Agbemenu ◽  
Eric Tchao ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Frequency Synthesizer ◽  
Complementary Metal Oxide Semiconductor ◽  
External Input ◽  
Oxide Semiconductor ◽  
Voltage Controlled Oscillator ◽  
Very High Frequency ◽  
Low Area ◽  
Self Test ◽  
Built In Self Test

Abstract This paper presents the design of an on-chip charge pump phase-locked loop (CP-PLL) with a fully digital defect oriented built-in self-test (BIST) for very-high frequency (VHF) applications. The frequency synthesizer has a 40 to 100 MHz tuning range and uses a ring voltage-controlled oscillator for frequency synthesis. The PLL exhibits a phase noise of -132 dBc/Hz at 1 MHz and consumes 1.8 mW on a 3 V supply. The BIST implementation uses fewer external input or output, is capable of efficient fault diagnosis, and is compact, posing a low area overhead. The integrated circuit design was realized in the AMI 0.6µ complementary metal oxide-semiconductor process.

DESIGN OF A FULLY INTEGRATED 2.4 GHz FREQUENCY PLL SYNTHESIZER FOR ZigBee TRANSCEIVER APPLICATION

2014 ◽  
Vol 23 (10) ◽  
pp. 1450137 ◽  
Author(s):  
DI LI ◽  
YINTANG YANG ◽  
DUAN ZHOU ◽  
YANI LI ◽  
XIAOPENG WU
Keyword(s):  
Frequency Synthesizer ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Frequency Resolution ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Amplitude Control ◽  
Fully Integrated ◽  
Automatic Amplitude Control ◽  
Metal Insulator Metal

A 2.4-GHz fully integrated frequency synthesizer is presented in this paper for Low-IF ZigBee (IEEE802.15.4) transceiver applications. The frequency synthesizer meets the system requirement of 2.4–2.4835 GHz frequency range with a frequency resolution of 5 MHz. The automatic-amplitude control (AAC) technique is employed for the voltage-controlled oscillator (VCO) which helps to optimize the output amplitude of the VCO over voltage, process and temperature variations. The chip has been fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process using a single poly layer, four metal layers and metal–insulator–metal (MIM) capacitors. The synthesized has a current dissipation of 4.7 mA from a 1.8 V power supply and occupies an area of 1 mm2 × 0.85 mm2. Measurement results show that the phase noise are -82 dBc/Hz–100 kHz offset and -109 dBc/Hz–1 MHz offset respectively.

Performance study of a 248 GHz voltage controlled hetero-integrated source in InP-on-BiCMOS technology

2015 ◽  
Vol 9 (2) ◽  
pp. 259-268
Author(s):  
Maruf Hossain ◽  
Ina Ostermay ◽  
Nils G. Weimann ◽  
Franz Josef Schmueckle ◽  
Johannes Borngraeber ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Frequency Multiplier ◽  
Oxide Semiconductor ◽  
Voltage Controlled Oscillator ◽  
Performance Study ◽  
Wafer Level ◽  
Bicmos Technology ◽  
Insertion Losses ◽  
Vertical Transitions

This paper presents the performance study of a 248 GHz voltage-controlled hetero-integrated signal source using indium phosphide (InP)-on-bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The source consists of a voltage controlled oscillator (VCO) in 0.25 µm BiCMOS technology and a frequency multiplier in 0.8 µm transferred-substrate InP-heterojunction bipolar transistor technology, which is integrated on top of the BiCMOS monolithic microwave integrated circuit in a wafer-level based benzocyclobutene bonding process. The vertical transitions from BiCMOS to InP in this process exhibit broadband properties with insertion losses below 0.5 dB up to 325 GHz. The VCO operates at 82.7 GHz with an output power of 6 dBm and the combined circuit delivers −9 dBm at 248 GHz with 1.22% tuning range. The phase noise of the combined circuit is −85 dBc/Hz at 1 MHz offset. The measured output return loss of the hetero-integrated source is >10 dB within a broad frequency range. This result shows the potential of the hetero integrated process for THz frequencies.

scholarly journals Effects of Process Variations in a HCMOS IC using a Monte Carlo SPICE Simulation

2017 ◽  
pp. 11-16
Author(s):  
Widianto Widianto ◽  
Lailis Syafaah ◽  
Nurhadi Nurhadi
Keyword(s):  
Monte Carlo ◽  
Integrated Circuit ◽  
High Speed ◽  
Evaluation Method ◽  
Complementary Metal Oxide Semiconductor ◽  
Process Variations ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Spice Simulation ◽  
Simulation Results

In this paper, effects of process variations in a HCMOS (High-Speed Complementary Metal Oxide Semiconductor) IC (Integrated Circuit) are examined using a Monte Carlo SPICE (Simulation Program with Integrated Circuit Emphasis) simulation. The variations of the IC are L and VTO variations. An evaluation method is used to evaluate the effects of the variations by modeling it using a normal (Gaussian) distribution. The simulation results show that the IC may be detected as a defective IC caused by the variations based on large supply currents flow to it. 

scholarly journals Angular Light, Polarization and Stokes Parameters Information in a Hybrid Image Sensor with Division of Focal Plane

Sensors ◽  
2020 ◽  
Vol 20 (12) ◽  
pp. 3391
Author(s):  
Francelino Freitas Carvalho ◽  
Carlos Augusto de Moraes Cruz ◽  
Greicy Costa Marques ◽  
Kayque Martins Cruz Damasceno
Keyword(s):  
Integrated Circuit ◽  
Incident Angle ◽  
Complementary Metal Oxide Semiconductor ◽  
Image Sensor ◽  
Light Polarization ◽  
Oxide Semiconductor ◽  
Stokes Parameters ◽  
New Paradigm ◽  
Depth Sensing ◽  
3D Image Reconstruction

Targeting 3D image reconstruction and depth sensing, a desirable feature for complementary metal oxide semiconductor (CMOS) image sensors is the ability to detect local light incident angle and the light polarization. In the last years, advances in the CMOS technologies have enabled dedicated circuits to determine these parameters in an image sensor. However, due to the great number of pixels required in a cluster to enable such functionality, implementing such features in regular CMOS imagers is still not viable. The current state-of-the-art solutions require eight pixels in a cluster to detect local light intensity, incident angle and polarization. The technique to detect local incident angle is widely exploited in the literature, and the authors have shown in previous works that it is possible to perform the job with a cluster of only four pixels. In this work, the authors explore three novelties: a mean to determine three of four Stokes parameters, the new paradigm in polarization cluster-pixel design, and the extended ability to detect both the local light angle and intensity. The features of the proposed pixel cluster are demonstrated through simulation program with integrated circuit emphasis (SPICE) of the regular Quadrature Pixel Cluster and Polarization Pixel Cluster models, the results of which are compliant with experimental results presented in the literature.

scholarly journals A 45 nm CMOS Avalanche Photodiode with 8.4-GHz Bandwidth

Micromachines ◽  
2020 ◽  
Vol 11 (1) ◽  
pp. 65
Author(s):  
Wenhao Zhi ◽  
Qingxiao Quan ◽  
Pingping Yu ◽  
Yanfeng Jiang
Keyword(s):  
Optical Communication ◽  
Integrated Circuit ◽  
Communication Systems ◽  
Complementary Metal Oxide Semiconductor ◽  
Avalanche Photodiode ◽  
Cmos Technology ◽  
Optical Signal ◽  
Oxide Semiconductor ◽  
Monolithically Integrated ◽  
Process Modification

Photodiode is one of the key components in optoelectronic technology, which is used to convert optical signal into electrical ones in modern communication systems. In this paper, an avalanche photodiode (APD) is designed and fulfilled, which is compatible with Taiwan Semiconductor Manufacturing Company (TSMC) 45-nm standard complementary metal–oxide–semiconductor (CMOS) technology without any process modification. The APD based on 45 nm process is beneficial to realize a smaller and more complex monolithically integrated optoelectronic chip. The fabricated CMOS APD operates at 850 nm wavelength optical communication. Its bandwidth can be as high as 8.4 GHz with 0.56 A/W responsivity at reverse bias of 20.8 V. Its active area is designed to be 20 × 20 μm2. The Simulation Program with Integrated Circuit Emphasis (SPICE) model of the APD is also proposed and verified. The key parameters are extracted based on its electrical, optical and frequency responses by parameter fitting. The device has wide potential application for optical communication systems.

scholarly journals Monolithic optoelectronic integrated broadband optical receiver with graphene photodetectors

Nanophotonics ◽  
2017 ◽  
Vol 6 (6) ◽  
pp. 1343-1352 ◽  
Author(s):  
Chuantong Cheng ◽  
Beiju Huang ◽  
Xurui Mao ◽  
Zanyun Zhang ◽  
Zan Zhang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Cost ◽  
Three Dimensional ◽  
Complementary Metal Oxide Semiconductor ◽  
Optical Signal ◽  
Optical Interconnect ◽  
Optical Receiver ◽  
Oxide Semiconductor ◽  
Experimental Realization ◽  
Operation Speed

AbstractOptical receivers with potentially high operation bandwidth and low cost have received considerable interest due to rapidly growing data traffic and potential Tb/s optical interconnect requirements. Experimental realization of 65 GHz optical signal detection and 262 GHz intrinsic operation speed reveals the significance role of graphene photodetectors (PDs) in optical interconnect domains. In this work, a novel complementary metal oxide semiconductor post-backend process has been developed for integrating graphene PDs onto silicon integrated circuit chips. A prototype monolithic optoelectronic integrated optical receiver has been successfully demonstrated for the first time. Moreover, this is a firstly reported broadband optical receiver benefiting from natural broadband light absorption features of graphene material. This work is a perfect exhibition of the concept of monolithic optoelectronic integration and will pave way to monolithically integrated graphene optoelectronic devices with silicon ICs for three-dimensional optoelectronic integrated circuit chips.

scholarly journals Fully Differential Chopper-Stabilized Multipath Current-Feedback Instrumentation Amplifier with R-2R DAC Offset Adjustment for Resistive Bridge Sensors

2019 ◽  
Vol 10 (1) ◽  
pp. 63 ◽  
Author(s):  
Yongsu Kwon ◽  
Hyungseup Kim ◽  
Jaesung Kim ◽  
Kwonsang Han ◽  
Donggeun You ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Current Feedback ◽  
Readout Integrated Circuit ◽  
Fully Differential ◽  
Chopper Stabilization ◽  
Rejection Ratio

A fully differential multipath current-feedback instrumentation amplifier (CFIA) for a resistive bridge sensor readout integrated circuit (IC) is proposed. To reduce the CFIA’s own offset and 1/f noise, a chopper stabilization technique is implemented. To attenuate the output ripple caused by chopper up-modulation, a ripple reduction loop (RRL) is employed. A multipath architecture is implemented to compensate for the notch in the chopping frequency band of the transfer function. To prevent performance degradation resulting from external offset, a 12-bit R-2R digital-to-analog converter (DAC) is employed. The proposed CFIA has an adjustable gain of 16–44 dB with 5-bit programmable resistors. The proposed resistive sensor readout IC is implemented in a 0.18 μm complementary metal-oxide-semiconductor (CMOS) process. The CFIA draws 169 μA currents from a 3.3 V supply. The simulated input-referred noise and noise efficiency factor (NEF) are 28.3 nV/√Hz and 14.2, respectively. The simulated common-mode rejection ratio (CMRR) is 162 dB, and the power supply rejection ratio (PSRR) is 112 dB.

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