scholarly journals A Review on IEEE-754 Standard Floating Point Multiplier using Vedic Mathematics

2021 ◽  
Vol 9 (VI) ◽  
pp. 1300-1303
Author(s):  
Rajesh Deokate
Keyword(s):  
Digital Signal ◽  
Digital Signal Processors ◽  
Floating Point ◽  
Standard Format ◽  
Processing Elements ◽  
Vedic Mathematics ◽  
One Step ◽  
Basic Functions ◽  
Step Generation ◽  
Signal Processors

The fundamental and the core of all the Digital Signal Processors (DSPs) are its multipliers and the speed of the DSPs is mainly determined by the speed of its multiplier. IEEE floating point format is a standard format used in all processing elements since Binary floating point numbers multiplication is one of the basic functions used in digital signal processing (DSP) application. In this work VHDL implementation of Floating Point Multiplier using Vedic mathematics is carried out. The Urdhva Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. Multiplication of two no’s using Urdhva Tiryakbhyam sutra is performed by vertically and crosswise. The feature is any multi-bit multiplication can be reduced down to single bit multiplication and addition using this method. On account of these formulas, the carry propagation from LSB to MSB is reduces due to one step generation of partial product.

scholarly journals An efficient floating-point multiplier for digital signal processors

2014 ◽  
Vol 11 (6) ◽  
pp. 20140078-20140078 ◽  
Author(s):  
Zonglin Liu ◽  
Sheng Ma ◽  
Yang Guo
Keyword(s):  
Digital Signal ◽  
Digital Signal Processors ◽  
Floating Point ◽  
Signal Processors

An Efficient Design of 16 Bit MAC Unit using Vedic Mathematics

2021 ◽  
pp. 1-4
Author(s):  
N. Manoj Kumar ◽  
◽  
G. Saravanan ◽  
D. Shyam Ganesh ◽  
S. Kanimozi ◽  
...  
Keyword(s):  
Digital Signal ◽  
Digital Signal Processors ◽  
Square Root ◽  
Efficient Design ◽  
Verilog Hdl ◽  
Vedic Mathematics ◽  
Vedic Multiplier ◽  
Game Plan ◽  
Signal Processors

Duplicate and Accumulate (MAC) is one of the central practices utilized absolutely in signal- controlling and different applications. The multiplier is the major piece of Digital Signal Processors (DSPs). Its cutoff spins around power, LUT use, and surrender pick the presence of a DSP. In like way, there is a need to sort out the drive and give up fit multiplier. In this paper, a 16-digit MAC unit is proposed to utilize an 8-cycle Vedic multiplier and pass on a save snake. A relationship with the current 8-cycle Vedic multiplier utilizing Square-Root (SQR) Carry-select snake (CSLA) is introduced. It is isolated and a standard pack multiplier. The whole technique is done in Verilog HDL. Blend and redirections were finished utilizing Xilinx InDesign Suite 14.5. The proposed game plan accomplishes fundamental improvement in region and suspension. In like manner, an abatement in power around 9.5% is refined.

scholarly journals A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors

2021 ◽  
Author(s):  
K Gavaskar ◽  
D Malathi ◽  
G Ravivarma ◽  
V Krithika Devi ◽  
M Megala ◽  
...  
Keyword(s):  
Mathematical Practice ◽  
Digital Signal ◽  
Structure Design ◽  
Digital Signal Processors ◽  
Parameter Analysis ◽  
Vedic Mathematics ◽  
Multiplication Process ◽  
Vedic Multiplier ◽  
Wallace Tree Multiplier ◽  
Signal Processors

Abstract The Multiply Accumulate (MAC) unit constructed using antiquated Vedic mathematical practice and the efficiency of the vertical and transversely of Vedic approach for multiplication, which gives a distinction in genuine cycle of Multiplier itself. Vedic-Mathematics is depend on 16-Sutras, in that Urdhva-Triyakbhyam (UT) more productive one. It literally means vertical and cross wise operations. It eliminates unwanted multiplication and allows the parallel creation of partial products and addition steps. The adders are utilized to append the partial-product generated in the Vedic mathematics methodology to drops the combinational lag. MAC is an essential unit in the digital signal processors, to show the characters like speed, power as well as area. Hence, finer multiplier plans are to increase the order of the system. The Modified sum product algorithm based Vedic multiplier is one such promising solution. It has a rapid multiplication process and reaches a less calculation complexity above its traditional multiplier. Array multiplier, Baugh-Wooley multiplier, Wallace-tree multiplier and Vedic multiplier were created in the existing work. In proposed work Vedic multiplier, using modified sum product algorithm was designed. The structure design coded in verilog and parameter analysis was done in Xilinx. The parameters like delay as well as power were compare between existing and proposed. When comparing with different multiplier with our proposed work delay get reduced. Comparing with existing multiplier the proposed 4x4 Vedic multiplier have 49.12% reduction in delay. Comparing with existing multiplier the proposed Vedic 4x4 multiplier have 42.51% reduction in power.

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