Simulation and Analysis of different CMOS Full Adders for Delay Optimisation

2021 ◽  
Vol 9 (9) ◽  
pp. 66-70
Author(s):  
Nakul C. Kubsad
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Digital Signal ◽  
Full Adder ◽  
Digital Signal Processors ◽  
Transmission Gate ◽  
Logical Operations ◽  
Recent Advancement ◽  
Voltage Swing ◽  
Signal Processors

Abstract: Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK – 180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay. Keywords: Delay, power dissipation, voltage, transistor sizing.

scholarly journals Two state-of-the-arts current-mode ternary full adders based on CNTFET Technology

2020 ◽  
Vol 9 (1) ◽  
pp. 19
Author(s):  
Mona Moradi
Keyword(s):  
Power Dissipation ◽  
Digital Signal ◽  
Current Mode ◽  
Full Adder ◽  
Vlsi Circuits ◽  
Digital Signal Processors ◽  
The Arts ◽  
Threshold Voltages ◽  
Static Power ◽  
Signal Processors

Adder core respecting to its various applications in VLSI circuits and<br />systems is considered as the most critical building block in microprocessors,<br />digital signal processors and arithmetic operations. Novel designs of a low<br />power and complexity Current Mode 1-bit Full Adder cell based on<br />CNTFET technology has been presented in this paper. Three major parts<br />construct their structures; 1) the first part that converts current to voltage; 2)<br />threshold detectors (TD); and 3) parallel paths to convey the output currents<br />flow. Adjusting threshold voltages which are significant factor for setting<br />threshold detectors switching point has been achieved by means of CNTFET<br />technology. It would bring significant improvements in adjusting threshold<br />voltages, regarding to its unique characterizations. Simple design, less<br />transistor counts and static power dissipation and better performance<br />comparing previous designs could be considered as some advantages of the<br />novel designs.

High Speed Vedic Multiplier for Digital Signal Processors

2009 ◽  
Vol 55 (6) ◽  
pp. 282 ◽  
Author(s):  
Ramesh Pushpangadan ◽  
Vineeth Sukumaran ◽  
Rino Innocent ◽  
Dinesh Sasikumar ◽  
Vaisak Sundar
Keyword(s):  
High Speed ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Vedic Multiplier ◽  
Signal Processors

scholarly journals Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor

2019 ◽  
Vol 9 (6) ◽  
pp. 4933-4936
Author(s):  
H. Ghabri ◽  
D. Ben Issa ◽  
H. Samet
Keyword(s):  
Performance Optimization ◽  
Field Effect Transistor ◽  
Digital Circuits ◽  
Digital Signal ◽  
Full Adder ◽  
Cmos Technology ◽  
Digital Signal Processors ◽  
Effect Transistor ◽  
Power Delay Product ◽  
Signal Processors

The full adder is a key component for many digital circuits like microprocessors or digital signal processors. Its main utilization is to perform logical and arithmetic operations. This has empowered the designers to continuously optimize this circuit and ameliorate its characteristics like robustness, compactness, efficiency, and scalability. Carbon Nanotube Field Effect Transistor (CNFET) stands out as a substitute for CMOS technology for designing circuits in the present-day technology. The objective of this paper is to present an optimized 1-bit full adder design based on CNTFET transistors inspired by new CMOS full adder design [1] with enhanced performance parameters. For a power supply of 0.9V, the count of transistors is decreased to 10 and the power is almost split in two compared to the best existing CNTFET based adder. This design offers significant improvement when compared to existing designs such as C-CMOS, TFA, TGA, HPSC, 18T-FA adder, etc. Comparative data analysis shows that there is 37%, 50%, and 49% amelioration in terms of area, delay, and power delay product respectively compared to both CNTFET and CMOS based adders in existing designs. The circuit was designed in 32nm technology and simulated with HSPICE tools.

scholarly journals Enhanced and Efficient Carry Select Adder with Minimal Delay

2021 ◽  
Author(s):  
G. Srividhya ◽  
T. Sivasakthi ◽  
R. Srivarshini ◽  
P. Varshaa ◽  
S. Vijayalakshmi
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Digital Signal ◽  
Propagation Delay ◽  
Digital Signal Processors ◽  
Digital World ◽  
Carry Select Adder ◽  
Image Processors ◽  
Improved Model ◽  
Signal Processors

In today’s digital world, Arithmetic computations have been evolved as a core factor in digital signal processors, micro-controllers, and systems using arithmetic and logical operations such as adders, multipliers, image processors, and signal processors. One of the elements that play an important role in performing arithmetic calculations is an adder. Among many adders, the Carry Select Adder produces less propagation delay. However, there may be an increased delay, power consumption, and area required in the case of a normal Carry Select Adder. To overcome the mentioned drawbacks, an improved model of Carry Select Adder has been designed that uses Binary to Excess – 1 Converter. Instead of using multiple blocks of Ripple Carry Adders (RCAs), it is efficient and effective if one of the blocks is replaced with Binary to Excess – 1 Converter. As a result, we can achieve a high speed adder with minimal delay, minimal power, and reduced area.

scholarly journals FPGA Based Vector Control of Induction Motor

2020 ◽  
Vol 9 (4) ◽  
pp. 572-577
Keyword(s):  
Induction Motor ◽  
High Speed ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Electronic Industry ◽  
New Approach ◽  
The Past ◽  
Field Programmable ◽  
Signal Processors ◽  
Very High

To get the desired response of the sensor less Vector controlled Induction Motor (SVC-IM) by the experimental setup, the controller implementation for the generation of the PWM signals is the key role. It is possible with the rapid growth of electronic industry such as high speed digital signal processors (DSPs) with micro controllers available in the present market. In the past DSP technologies were used to realize the several SVC-IM schemes, i.e. KF, PI, GA and PSO respectively. However, it creates issues related to the time delay and execution of the PWM signals, etc., as a results system becomes complex. Therefore a new approach is implemented to overcome the issues related to the execution time, namely Field Programmable Gate Array (FPGA) processors are suggested in the present market. Moreover the programming is done using very high speed hardware descriptive language (VHDL)

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

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