scholarly journals 4-bit Carry Look Ahead Adder Using MGDI Technique

2021 ◽  
Vol 9 (9) ◽  
pp. 855-860
Author(s):  
Shaik Mahammad Ameer Afridi
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Power Dissipation ◽  
High Performance ◽  
Digital Signal ◽  
Vlsi Circuits ◽  
Digital Vlsi ◽  
Look Ahead ◽  
Energy Trade ◽  
Integral Role

Abstract: Today's high-performance processor is built with arithmetic logic units that add and subtract key components. Design considerations related to low power and high performance digital VLSI circuits have become more prevalent in today's world. In order to develop low-power and high-performance processors, the designers need to design their adder circuits with the required speed and power dissipation for their applications. This topic introduces the concept of a adder using MGDI Technique. The Exact Speculative Carry Look Ahead Adder the use of the Modified-GDI (Modified-Gate Diffusion Input) is cautioned in this work. The delay, location and energy trade off performs a integral role in VLSI. We already comprehend that designs which are of CMOS fashion occupy extra area might also eat extra strength consumption. The switching conduct of the circuit reason the heating up of integrated circuits affects the working stipulations of the purposeful unit. The adders are the most important parts of countless applications such as microprocessors, microcontrollers and digital signal processors and additionally in actual time applications. Hence it is necessary to minimize the adder blocks to format a perfect processor. This work is proposed on a 16 bit carry seem to be in advance adder is designed through using MGDI gate and 4T XOR gates and a speculator blocks. The proposed MGDI raise Look Ahead adder occupies 68% much less region and the strength consumption and the propagation extend additionally considerably reduces when in contrast to the traditional carry Look Ahead adder why because the variety transistors extensively reduces from 1448 (Conventional) to 456 (Proposed CLA). The simulation consequences of the proposed format carried out in Xilinx. Keywords: Delay, power dissipation, voltage, transistor sizing.

Novel Nanometric Reversible Low Power Bidirectional Universal Logarithmic Barrel Shifter with Overflow and Zero Flags

2015 ◽  
Vol 24 (04) ◽  
pp. 1550049 ◽  
Author(s):  
Nayereh Hosseininia ◽  
Soudabeh Boroumand ◽  
Majid Haghparast
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Error Control ◽  
Digital Signal ◽  
General Purpose ◽  
Vlsi Circuits ◽  
Quantum Cost ◽  
Hardware Complexity ◽  
Barrel Shifter

One of the most important issues in designing VLSI circuits is power consumption. Reversible logic which is widely utilized in quantum computing, low power CMOS design, optical information processing, bioinformatics and nanotechnology-based systems decreases power loss. A reversible circuit has zero internal power dissipation because it does not lose information. Reversible barrel shifters are required to construct reversible embedded digital signal and general-purpose processors. Data shifting is often used in high-speed/low-power error-control applications, floating point normalization, address decoding and bit indexing. This paper proposes a novel reversible bidirectional universal barrel shifter which is applied in high speed and high performance applications. The proposed barrel shifter is designed in a single circuit with overflow and zero flags. It performs three operations consisting of rotating, logical and arithmetic shifting that transfers and shifts data in both directions. The design is evaluated and formulated in terms of number of garbage outputs, number of constant inputs, quantum cost, number of reversible gates and hardware complexity. All the scales are in nanometric area.

Analytical Study Of Full Adder Circuit Using Modified Glitch Free Cascadable Adiabatic Logic

2018 ◽  
Vol 3 (2) ◽  
Author(s):  
Neha Raghav ◽  
◽  
Malti Bansal
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Performance ◽  
Analytical Study ◽  
Supply Voltage ◽  
Full Adder ◽  
Vlsi Circuits ◽  
Low Power Consumption ◽  
Adiabatic Logic

Nowadays, power dissipation is among the most dominant concerns in designing a VLSI circuits. Endless improvement in technology has points to an increased requirement for devices which have the basic characteristic of low power consumption. Hence power has turn into a demanding design parameter in low power and high-performance applications. The Adiabatic logic technique is becoming a solution to the dilemma of power dissipation. Adders with huge power consumption affect the overall efficiency of the system. Hence, in this paper, the proposed application of full adder circuit is shown using the Modified Glitch Free Cascadable Adiabatic Logic. The circuit is compared with the conventional CMOS Logic and the power dissipation analysis is simulated with supply voltage = 0.9 V, 1.2 V and 1.8 V to analyze the pattern followed with supply variation at different temperature range. Similarly, the calculation of delay is performed for temperature values of 27˚C, 55˚C and 120˚C at 90nm technology.

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

scholarly journals Analysis On Power Gating Circuits Based Low Power VLSI Circuits (BCD Adder)

2021 ◽  
Vol 2089 (1) ◽  
pp. 012080
Author(s):  
M. Srinivas ◽  
K.V. Daya Sagar
Keyword(s):  
Energy Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Battery Life

Abstract Currently, energy consumption in the digital circuit is a key design parameter for emerging mobile products. The principal cause of the power dissipation during idle mode is leakage currents, which are rising dramatically. Sub-threshold leakage is increased by the scaling of threshold voltage when gate current leakage increases because oxide thickness is scaled. With rising demands for mobile devices, leakage energy consumption has received even greater attention. Since a mobile device spends most of its time in standby mode, leakage power savings need to prolong the battery life. That is why low power has become a significant factor in CMOS circuit design. The required design and simulation of an AND gate with the BSIM4 MOS parameter model at 27 0C, supply voltage of 0,70V with CMOS technology of 65nm are the validation of the suitability of the proposed circuit technology. AND simulation. The performance parameters for the two AND input gate are compared with the current MTCMOS and SCCMOS techniques, such as sub-threshold leakage power dissipations in active and standby modes, the dynamic dissipation, and propagation period. The proposed hybrid super cutoff complete stack technique compared to the current MTCMOS technology shows a reduction in sub-threshold dissipation power dissipation by 3. 50x and 1.15x in standby modes and active modes respectively. The hybrid surface-cutting technique also shows savings of 2,50 and 1,04 in power dissipation at the sub-threshold in standby modes and active modes compared with the existing SCCMOS Technique.

scholarly journals Modified Low Power Binary to Excess Code Converter

2015 ◽  
Vol 4 (03) ◽  
pp. 06-10
Author(s):  
Ms. Mayuri Ingole
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Performance ◽  
Major Aspect ◽  
Code Converter ◽  
Ripple Carry Adder ◽  
Carry Select Adder ◽  
The One

Utilization of power is a major aspect in the design of integrated circuits. Since, adders are mostly employed in these circuits, we should design them effectively. Here, we propose an easy and effective method in decreasing the maximum consumption of power. Carry Select Adder is the one which is dependent on the design of two adders. We present a high performance low-power adder that is implemented. Also, here in Carry Select Adder, Binary Excess Code-1is replaced by Ripple Carry Adder. After analyzing the results, we can come to a conclusion that the architecture which is proposed will have better results in terms of consumption of power compared to conventional techniques. 

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Low Power ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
State Dependency ◽  
Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

scholarly journals A Glitch-Free Novel DET-FF in 22 nm CMOS for Low-Power Application

2018 ◽  
Vol 2018 ◽  
pp. 1-6 ◽  
Author(s):  
Sumitra Singar ◽  
N. K. Joshi ◽  
P. K. Ghosh
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Vlsi Design ◽  
Total System ◽  
Clock Frequency ◽  
Flip Flop ◽  
Digital Vlsi ◽  
Feedback Structure ◽  
Power Application

Dual edge triggered (DET) techniques are most liked choice for the researchers in the field of digital VLSI design because of its high-performance and low-power consumption standard. Dual edge triggered techniques give the similar throughput at half of the clock frequency as compared to the single edge triggered (SET) techniques. Dual edge triggered techniques can reduce the 50% power consumption and increase the total system power savings. The low-power glitch-free novel dual edge triggered flip-flop (DET-FF) design is proposed in this paper. Still now, existing DET-FF designs are constructed by using either C-element circuit or 1P-2N structure or 2P-1N structure, but the proposed novel design is designed by using the combination of C-element circuit and 2P-1N structure. In this design, if any glitch affects one of the structures, then it is nullified by the other structure. To control the input loading, the two circuits are merged to share the transistors connected to the input. In the proposed design, we have used an internal dual feedback structure. The proposed design reduces the delay and power consumption and increases the speed and efficiency of the system.

Modified Operand Decomposition Multiplication for High Performance Parallel Multipliers

2016 ◽  
Vol 25 (12) ◽  
pp. 1650149 ◽  
Author(s):  
Z. Abid ◽  
Dalia A. El-Dib ◽  
Rizwan Mudassir
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Performance ◽  
Energy Delay Product

A low power operand decomposition multiplication architecture implementation is modified to further reduce its power dissipation and delay. First, the multiplier’s implementation was modified to generate the partial products using NAND gates instead of AND and OR gates in order to reduce the number of transistors (area utilized) and to reduce the delay. Then, new types of adders and (4:2) compressors, that accept negatively weighted bits are used to reduce the number of inverters. Therefore, the resulting multiplier architecture reduces the number of transistors significantly. These modifications result in 20% and 36% reduction in power consumption and energy delay product (EDP), respectively.

Buffer for High Performance in CNT Based VLSI Interconnects

2018 ◽  
Vol 24 (8) ◽  
pp. 5975-5981
Author(s):  
A Karthikeyan ◽  
P. S Mallick
Keyword(s):  
Integrated Circuits ◽  
Packing Density ◽  
Power Dissipation ◽  
High Performance ◽  
Critical Path ◽  
Vlsi Interconnects ◽  
Performance Constraints ◽  
Interconnect Delay ◽  
Interconnect Optimization ◽  
Technology Nodes

Integrated circuits (IC’s) are sized for higher performance and packing density. Interconnects are major components to carry signals between transistors. Interconnect delay increases due to increase in length of interconnect. Optimization of interconnects is more essential to improve the performance of integrated circuits. Repeater insertion is an important technique used in optimizing the performance of interconnects in integrated circuits. Repeaters have to be designed to satisfy the performance constraints. In this paper we have designed a new repeater using transistors and analyzed the performance at various bias levels. The Repeater design was implemented at various technology nodes using PTM models and Bulk CMOS. Delay and power dissipation are analyzed for various voltage levels and load levels using Spice simulations. The results show that the proposed repeater has lesser delay compared to the conventional repeater with an increase of power dissipation and they are more suitable for Critical path in VLSI interconnects. They can be applicable for CNT based VLSI interconnects.

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