Memory Requirement Reduction of Deep Neural Networks for Field Programmable Gate Arrays Using Low-Bit Quantization of Parameters

2021 ◽  
Author(s):  
Niccolo Nicodemo ◽  
Gaurav Naithani ◽  
Konstantinos Drossos ◽  
Tuomas Virtanen ◽  
Roberto Saletti
Keyword(s):  
Neural Networks ◽  
Deep Neural Networks ◽  
Field Programmable Gate Arrays ◽  
Memory Requirement ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

scholarly journals Design and Implementation of Perceptron Neuron in Machine Learning for Handwritten Character Recognition

2020 ◽  
Vol 9 (10) ◽  
pp. 357-363
Keyword(s):  
Machine Learning ◽  
Neural Networks ◽  
Feature Extraction ◽  
Field Programmable Gate Arrays ◽  
Fpga Implementation ◽  
Floating Point ◽  
Neuron Network ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

Due to the exponential increase of electronic devices that are connected to the Internet, the amount of data that they produce have grown to the same extent. In order to face the processing of these data, the use of some automatic learning algorithms, also known as Machine Learning, has become widespread. The most popular is the one known as neural networks. These algorithms need a great deal of resources to compute all their operations, and because of that, they have been traditionally implemented in application specific integrated circuits. However, recently there have been a boom in implementations in field programmable gate arrays, also known as FPGAs. These allow greater parallelism in the implementation of the algorithms. Field Programmable Gate Arrays (FPGA) implementation based feature extraction method is proposed in this paper. This particular application is handwritten offline digit recognition. The classification depends on simple 2 layer MultiLayer Perceptron (MLP). The particular feature extraction approach is suitable for execution of FPGA because it is utilized with subtraction and addition operations. From Standard database handwritten digit images of normalized 40×40 pixel the features are extracted by the proposed method. It has been discovered by experiential outcomes that 85% accuracy is achieved by proposed system. Overall, as compared to other systems, it is less complex, more accurate and simple. Further this project explains IEE-754 format single precision floating point MAC unit’s FPGA implementation which is utilized for feeding the neurons weighted inputs in artificial neural networks. Data representation range is improved by floating point numbers utilization to a higher number from smaller number that is highly suggested for Artificial Neuron Network. The code is developed in HDL, simulated and synthesis results are extracted using Xilinx synthesis tools .In order to validate its computational accuracy of the FFT, an MATLAB validation script is used to verify the output of HDL with standard reference model.

scholarly journals RTN: Reparameterized Ternary Network

2020 ◽  
Vol 34 (04) ◽  
pp. 4780-4787
Author(s):  
Yuhang Li ◽  
Xin Dong ◽  
Sai Qian Zhang ◽  
Haoli Bai ◽  
Yuanpeng Chen ◽  
...  
Keyword(s):  
Deep Neural Networks ◽  
State Of The Art ◽  
Hardware Acceleration ◽  
Field Programmable Gate Arrays ◽  
Accuracy Improvement ◽  
Gate Arrays ◽  
Resource Limited ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Speed Up

To deploy deep neural networks on resource-limited devices, quantization has been widely explored. In this work, we study the extremely low-bit networks which have tremendous speed-up, memory saving with quantized activation and weights. We first bring up three omitted issues in extremely low-bit networks: the squashing range of quantized values; the gradient vanishing during backpropagation and the unexploited hardware acceleration of ternary networks. By reparameterizing quantized activation and weights vector with full precision scale and offset for fixed ternary vector, we decouple the range and magnitude from direction to extenuate above problems. Learnable scale and offset can automatically adjust the range of quantized values and sparsity without gradient vanishing. A novel encoding and computation pattern are designed to support efficient computing for our reparameterized ternary network (RTN). Experiments on ResNet-18 for ImageNet demonstrate that the proposed RTN finds a much better efficiency between bitwidth and accuracy and achieves up to 26.76% relative accuracy improvement compared with state-of-the-art methods. Moreover, we validate the proposed computation pattern on Field Programmable Gate Arrays (FPGA), and it brings 46.46 × and 89.17 × savings on power and area compared with the full precision convolution.

scholarly journals FPGA-Based Controller for a Hybrid Grid-Connected PV/Wind/Battery Power System with AC Load

Energies ◽  
2021 ◽  
Vol 14 (8) ◽  
pp. 2108
Author(s):  
Mohamed Yassine Allani ◽  
Jamel Riahi ◽  
Silvano Vergura ◽  
Abdelkader Mami
Keyword(s):  
Fuzzy Logic ◽  
Hybrid System ◽  
High Voltage ◽  
Field Programmable Gate Arrays ◽  
Energy System ◽  
Maximum Power ◽  
Hybrid Energy ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

The development and optimization of a hybrid system composed of photovoltaic panels, wind turbines, converters, and batteries connected to the grid, is first presented. To generate the maximum power, two maximum power point tracker controllers based on fuzzy logic are required and a battery controller is used for the regulation of the DC voltage. When the power source varies, a high-voltage supply is incorporated (high gain DC-DC converter controlled by fuzzy logic) to boost the 24 V provided by the DC bus to the inverter voltage of about 400 V and to reduce energy losses to maximize the system performance. The inverter and the LCL filter allow for the integration of this hybrid system with AC loads and the grid. Moreover, a hardware solution for the field programmable gate arrays-based implementation of the controllers is proposed. The combination of these controllers was synthesized using the Integrated Synthesis Environment Design Suite software (Version: 14.7, City: Tunis, Country: Tunisia) and was successfully implemented on Field Programmable Gate Arrays Spartan 3E. The innovative design provides a suitable architecture based on power converters and control strategies that are dedicated to the proposed hybrid system to ensure system reliability. This implementation can provide a high level of flexibility that can facilitate the upgrade of a control system by simply updating or modifying the proposed algorithm running on the field programmable gate arrays board. The simulation results, using Matlab/Simulink (Version: 2016b, City: Tunis, Country: Tunisia, verify the efficiency of the proposed solution when the environmental conditions change. This study focused on the development and optimization of an electrical system control strategy to manage the produced energy and to coordinate the performance of the hybrid energy system. The paper proposes a combined photovoltaic and wind energy system, supported by a battery acting as an energy storage system. In addition, a bi-directional converter charges/discharges the battery, while a high-voltage gain converter connects them to the DC bus. The use of a battery is useful to compensate for the mismatch between the power demanded by the load and the power generated by the hybrid energy systems. The proposed field programmable gate arrays (FPGA)-based controllers ensure a fast time response by making control executable in real time.

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